From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x92d.google.com (mail-ua1-x92d.google.com [IPv6:2607:f8b0:4864:20::92d]) by sourceware.org (Postfix) with ESMTPS id E4B653858404 for ; Wed, 19 Apr 2023 12:21:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E4B653858404 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x92d.google.com with SMTP id v18so11350003uak.8 for ; Wed, 19 Apr 2023 05:21:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681906893; x=1684498893; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=z8rk2ifphNVXIFQOJ43pDxA+qXHKf88YRD99rDqLDS0=; b=A2iJ4eObv0Y/9BtcOszbO08o29J211pOJk6BS9ibjDiNMQpIYaa7KOmlk7iQzMwNX2 Ptlgj+1zvD4s9snOovmPve3Sk8S1LGl9hOLDELsat5jR9FjCFCDrpz6EbUJAqceKbhXi 6Wt5iCQQCaIcJaZIWTaLbtni968E+pl8+4WzhVyp5MiNKkUjEm+7sW+UXfB1xQ7LIcrZ lyfKFS6oO3v7DV7mLCgQcZUVrxY5BnHQW0QYEdN2YGWpQHPcXwkNAFcb1yHMHHhpfejO 5Spb8sv+OcDmwEbmzV+UyoQAoH+tOJThDq982lULXEtZWk6NAoAF5noB8lkYEtOM+x8n 4rcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681906893; x=1684498893; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=z8rk2ifphNVXIFQOJ43pDxA+qXHKf88YRD99rDqLDS0=; b=YyPQjsiROC83yFZx77wfbSEUKzYkP91wC7T3NOMATmjy+75Nu2KYoZpiu/ffcPuktG uw29knsE5mZ3kRSe+jIoEZPRNph547mf+NrmvKW9itD89g/9J8SJigPy/aH19bvQyZxe zyH5G0fco9BINHI9MMa3yh2WX+UkoKOIpmdthQr/bDlfPtX6Xe0tlGIo6ZJLTgTqzsZv ri9DILvTZxu5KZzWxugdzUkuVuEgCDf9TALK+OEGQUSBmAf8L8dFYcng8P8JCDqC4IHS qQCctlszsmt/GDP9Jb8JF/Q89Zy1iGPAuFHcqdzAfyUH3+vahiFgtZCr7gA6PXjK0Tey H+vw== X-Gm-Message-State: AAQBX9f6P/Ff+du6ms5hEUWkc71C7HrZ3D4Qdk7F7vcElYEf5p6xSijI 9/8hnGvd8T6eUL5Pti9bM6n3WPLBlibKky/TyOkfapoHwvkFrg== X-Google-Smtp-Source: AKy350an+dMjU7VEz/ZFz48USJoZaRzGerSRfsG6+l8GpfNsu0V5d3yjrNsb2SBFmATQtCKR+uRRvdQEuIl3jO85FR0= X-Received: by 2002:a1f:bf41:0:b0:43f:c8d3:e4c0 with SMTP id p62-20020a1fbf41000000b0043fc8d3e4c0mr7653278vkf.3.1681906893005; Wed, 19 Apr 2023 05:21:33 -0700 (PDT) MIME-Version: 1.0 References: <20230414014518.15458-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230414014518.15458-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Wed, 19 Apr 2023 20:21:21 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Support chunk 128 To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Could you add more description? maybe like this: RISC-V has provide different VLEN configuration by different ISA extension like `zve32x`, `zve64x` and `v` zve32x just guarantee the minimal VLEN is 32 bits, zve64x guarantee the minimal VLEN is 64 bits, and v guarantee the minimal VLEN is 128 bits, Current status (without this patch): Zve32x: Mode for one vector register mode is VNx1SImode and VNx1DImode is invalid mode - one vector register could hold 1 + 1x SImode where x is 0~n, so it might hold just one SI Zve64x: Mode for one vector register mode is VNx1DImode or VNx2SImode - one vector register could hold 1 + 1x DImode where x is 0~n, so it might hold just one DI. - one vector register could hold 2 + 2x SImode where x is 0~n, so it might hold just two SI. However `v` extension guarantees the minimal VLEN is 128 bits. We introduce another type/mode mapping for this configure: v: Mode for one vector register mode is VNx2DImode or VNx4SImode - one vector register could hold 2 + 2x DImode where x is 0~n, so it will hold at least two DI - one vector register could hold 4 + 4x SImode where x is 0~n, so it will hold at least four DI This patch model the mode more precisely for the RVV, and help some middle-end optimization that assume number of element must be a multiple of two.