From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe33.google.com (mail-vs1-xe33.google.com [IPv6:2607:f8b0:4864:20::e33]) by sourceware.org (Postfix) with ESMTPS id 1B9FB3858C78 for ; Thu, 20 Jul 2023 02:16:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1B9FB3858C78 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe33.google.com with SMTP id ada2fe7eead31-440bb9bad3cso143609137.0 for ; Wed, 19 Jul 2023 19:16:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689819391; x=1690424191; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=n/+5jQGY1ISGbYEwr3H4aNHw8OcTgx5SY5MQHT30SoE=; b=BO2DX2u8F/OwrAsoYfu/gVy5+NJLKd515ksI0Rk7wz/jOVPJRAxBXleY3fEZ4S8DFt qgiLC52ZVOr/p3jG1mG9yrSB8y4tHmqTl9AIUJ4s54AQ9R69ZiPqzUqrxYcL2qpW3PPD IE/tFHfMkEnmk+wMbF0RkRJd50FG5qF6nnSrfdsGnlFoCxFVftwLWqC3k9lzovI34XgE EKiyr77JhLqHZSNA8XOLEenXuVPPL4h9geTRwcq87y7E+SZpRqgRZ+2Jj/ZxnU89Q9TK QWJIjlmEsbiEEAfR+SVPNS5Oy7+FXFKPeQ316IugJXD/BMHlbrqPmG6qtYUVFvoun18y Lumw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689819391; x=1690424191; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=n/+5jQGY1ISGbYEwr3H4aNHw8OcTgx5SY5MQHT30SoE=; b=DbmpOAO8zUbP0/XupZEuESEa86GSbPEzs+xsMB6r6Ci+Eh0LOgcYlrpq+bHx/Gb9KJ ZbKpm4AjB1gHsi6K7dCQHl4fP4FIHOrwlZNIzISKaEKnBhWh+817nfa/l7doAi7PSfoA chR+YixAv9Xe7bh2ZKeTphnPESZyBGVCh+9RK5CZTNO9QCMEqrfUebVdwOpWxJYywhMo i/zvSsCgywCRWPYrun71cAFMWegzk7aqlKalTLw7lE3+ojAmrPp0fmD71v2B8cM+vdAg 9XABvPBEYJlREAhgqamB8goYEAJm75i0UWq5Ub65oOeW9f366Cq0qkUxGISUM91xJU4j 3DoA== X-Gm-Message-State: ABy/qLa0cTxat1EqwilvgptRkR1e49EzQ8mIDrWxn6sr0WzkZ0jjqrdR UFC+EAUy4PqfVmddeq6BBCau8UcT62x5UTgQqvY= X-Google-Smtp-Source: APBJJlHMkDoI66HgDlgCNqsDdBC9yg+UJ+smL2tuhxyqrvCkv1HjCSU7gAvXdXqG4DPqdkI7XVHZ/ZJYMpKRRDYkK/I= X-Received: by 2002:a67:f98b:0:b0:443:5ff0:bab2 with SMTP id b11-20020a67f98b000000b004435ff0bab2mr486009vsq.22.1689819390755; Wed, 19 Jul 2023 19:16:30 -0700 (PDT) MIME-Version: 1.0 References: <20230719232120.80316-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230719232120.80316-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Thu, 20 Jul 2023 10:16:18 +0800 Message-ID: Subject: Re: [PATCH V3] RISC-V: Refactor RVV machine modes To: Juzhe-Zhong Cc: GCC Patches , Kito Cheng , Robin Dapp , Jeff Law Content-Type: multipart/alternative; boundary="000000000000854c750600e1bc32" X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000854c750600e1bc32 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LGTM, I must say the number of modifications is less than my expect :) And it's a really big move for RVV implementation! Juzhe-Zhong =E6=96=BC 2023=E5=B9=B47=E6=9C=8820=E6= =97=A5 =E9=80=B1=E5=9B=9B 07:22 =E5=AF=AB=E9=81=93=EF=BC=9A > Current machine modes layout is hard to maintain && read && understand. > > For a LMUL =3D 1 SI vector mode: > 1. VNx1SI mode when TARGET_MIN_VLEN =3D 32. > 2. VNx2SI mode when TARGET_MIN_VLEN =3D 64. > 3. VNx4SI mode when TARGET_MIN_VLEN =3D 128. > > Such implementation produces redundant machine modes and thus redudant > machine description patterns. > > Now, this patch refactor machine modes into 3 follow formats: > > 1. mask mode: RVVMF64BImode, RVVMF32BImode, ...., RVVM1BImode. > RVVMF64BImode means such mask mode occupy 1/64 of a RVV M1 > reg. > RVVM1BImode size =3D LMUL =3D 1 reg. > 2. non-tuple vector modes: > RVV: E.g. RVVMF8QImode =3D SEW =3D 8 && = LMUL > =3D MF8 > 3. tuple vector modes: > RVVx. > > For example, for SEW =3D 16, LMUL =3D MF2 , int mode is always RVVMF4HImo= de, > then adjust its size according to TARGET_MIN_VLEN. > > Before this patch, the machine description patterns: 17551 > After this patch, the machine description patterns: 14132 =3D=3D=3D=3D=3D= > reduce > 3K+ patterns. > > Regression of gcc/g++ rv32/rv64 all passed. > > Ok for trunk? > > gcc/ChangeLog: > > * config/riscv/autovec.md > (len_mask_gather_load): Refactor RVV > machine modes. > (len_mask_gather_load): Ditto. > (len_mask_gather_load): Ditto. > (len_mask_gather_load): Ditto. > (len_mask_gather_load): Ditto. > (len_mask_gather_load): Ditto. > (len_mask_gather_load): Ditto. > (len_mask_scatter_store): Ditt= o. > (len_mask_scatter_store): Ditto. > (len_mask_scatter_store): Ditto. > (len_mask_scatter_store): Ditto. > (len_mask_scatter_store): Ditto. > (len_mask_scatter_store): Ditto. > (len_mask_scatter_store): Ditto. > * config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Ditto. > (ADJUST_NUNITS): Ditto. > (ADJUST_ALIGNMENT): Ditto. > (ADJUST_BYTESIZE): Ditto. > (ADJUST_PRECISION): Ditto. > (RVV_MODES): Ditto. > (RVV_WHOLE_MODES): Ditto. > (RVV_FRACT_MODE): Ditto. > (RVV_NF8_MODES): Ditto. > (RVV_NF4_MODES): Ditto. > (VECTOR_MODES_WITH_PREFIX): Ditto. > (VECTOR_MODE_WITH_PREFIX): Ditto. > (RVV_TUPLE_MODES): Ditto. > (RVV_NF2_MODES): Ditto. > (RVV_TUPLE_PARTIAL_MODES): Ditto. > * config/riscv/riscv-v.cc (struct mode_vtype_group): Ditto. > (ENTRY): Ditto. > (TUPLE_ENTRY): Ditto. > (get_vlmul): Ditto. > (get_nf): Ditto. > (get_ratio): Ditto. > (preferred_simd_mode): Ditto. > (autovectorize_vector_modes): Ditto. > * config/riscv/riscv-vector-builtins.cc (DEF_RVV_TYPE): Ditto. > * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): Ditto. > (vbool64_t): Ditto. > (vbool32_t): Ditto. > (vbool16_t): Ditto. > (vbool8_t): Ditto. > (vbool4_t): Ditto. > (vbool2_t): Ditto. > (vbool1_t): Ditto. > (vint8mf8_t): Ditto. > (vuint8mf8_t): Ditto. > (vint8mf4_t): Ditto. > (vuint8mf4_t): Ditto. > (vint8mf2_t): Ditto. > (vuint8mf2_t): Ditto. > (vint8m1_t): Ditto. > (vuint8m1_t): Ditto. > (vint8m2_t): Ditto. > (vuint8m2_t): Ditto. > (vint8m4_t): Ditto. > (vuint8m4_t): Ditto. > (vint8m8_t): Ditto. > (vuint8m8_t): Ditto. > (vint16mf4_t): Ditto. > (vuint16mf4_t): Ditto. > (vint16mf2_t): Ditto. > (vuint16mf2_t): Ditto. > (vint16m1_t): Ditto. > (vuint16m1_t): Ditto. > (vint16m2_t): Ditto. > (vuint16m2_t): Ditto. > (vint16m4_t): Ditto. > (vuint16m4_t): Ditto. > (vint16m8_t): Ditto. > (vuint16m8_t): Ditto. > (vint32mf2_t): Ditto. > (vuint32mf2_t): Ditto. > (vint32m1_t): Ditto. > (vuint32m1_t): Ditto. > (vint32m2_t): Ditto. > (vuint32m2_t): Ditto. > (vint32m4_t): Ditto. > (vuint32m4_t): Ditto. > (vint32m8_t): Ditto. > (vuint32m8_t): Ditto. > (vint64m1_t): Ditto. > (vuint64m1_t): Ditto. > (vint64m2_t): Ditto. > (vuint64m2_t): Ditto. > (vint64m4_t): Ditto. > (vuint64m4_t): Ditto. > (vint64m8_t): Ditto. > (vuint64m8_t): Ditto. > (vfloat16mf4_t): Ditto. > (vfloat16mf2_t): Ditto. > (vfloat16m1_t): Ditto. > (vfloat16m2_t): Ditto. > (vfloat16m4_t): Ditto. > (vfloat16m8_t): Ditto. > (vfloat32mf2_t): Ditto. > (vfloat32m1_t): Ditto. > (vfloat32m2_t): Ditto. > (vfloat32m4_t): Ditto. > (vfloat32m8_t): Ditto. > (vfloat64m1_t): Ditto. > (vfloat64m2_t): Ditto. > (vfloat64m4_t): Ditto. > (vfloat64m8_t): Ditto. > * config/riscv/riscv-vector-switch.def (ENTRY): Ditto. > (TUPLE_ENTRY): Ditto. > * config/riscv/riscv-vsetvl.cc (change_insn): Ditto. > * config/riscv/riscv.cc (riscv_valid_lo_sum_p): Ditto. > (riscv_v_adjust_nunits): Ditto. > (riscv_v_adjust_bytesize): Ditto. > (riscv_v_adjust_precision): Ditto. > (riscv_convert_vector_bits): Ditto. > * config/riscv/riscv.h (riscv_v_adjust_nunits): Ditto. > * config/riscv/riscv.md: Ditto. > * config/riscv/vector-iterators.md: Ditto. > * config/riscv/vector.md > (@pred_indexed_store): Ditto. > (@pred_indexed_store): > Ditto. > (@pred_indexed_store): > Ditto. > (@pred_indexed_store): Ditt= o. > (@pred_indexed_store): Ditt= o. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_load): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > (@pred_indexed_store): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c: > Adapt test. > * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c: > Ditto. > * > gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-9.c: Ditto. > * > gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c: > Ditto. > * > gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c: Ditto. > > --- > gcc/config/riscv/autovec.md | 198 +- > gcc/config/riscv/riscv-modes.def | 570 ++--- > gcc/config/riscv/riscv-v.cc | 67 +- > gcc/config/riscv/riscv-vector-builtins.cc | 15 +- > gcc/config/riscv/riscv-vector-builtins.def | 361 ++- > gcc/config/riscv/riscv-vector-switch.def | 581 ++--- > gcc/config/riscv/riscv-vsetvl.cc | 24 +- > gcc/config/riscv/riscv.cc | 87 +- > gcc/config/riscv/riscv.h | 1 + > gcc/config/riscv/riscv.md | 87 +- > gcc/config/riscv/vector-iterators.md | 2236 ++++++++--------- > gcc/config/riscv/vector.md | 826 +++--- > .../gather-scatter/gather_load_run-7.c | 6 +- > .../gather-scatter/gather_load_run-8.c | 6 +- > .../gather-scatter/mask_scatter_store-9.c | 5 + > .../gather-scatter/mask_scatter_store_run-8.c | 6 +- > .../gather-scatter/scatter_store_run-8.c | 6 +- > 17 files changed, 2496 insertions(+), 2586 deletions(-) > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index cd5b19457f8..00947207f3f 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -61,105 +61,90 @@ > ;; =3D=3D Gather Load > ;; > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > -(define_expand "len_mask_gather_load" > - [(match_operand:VNX1_QHSD 0 "register_operand") > +(define_expand "len_mask_gather_load" > + [(match_operand:RATIO64 0 "register_operand") > (match_operand 1 "pmode_reg_or_0_operand") > - (match_operand:VNX1_QHSDI 2 "register_operand") > - (match_operand 3 "") > - (match_operand 4 "") > + (match_operand:RATIO64I 2 "register_operand") > + (match_operand 3 "") > + (match_operand 4 "") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, true); > DONE; > }) > > -(define_expand "len_mask_gather_load" > - [(match_operand:VNX2_QHSD 0 "register_operand") > +(define_expand "len_mask_gather_load" > + [(match_operand:RATIO32 0 "register_operand") > (match_operand 1 "pmode_reg_or_0_operand") > - (match_operand:VNX2_QHSDI 2 "register_operand") > - (match_operand 3 "") > - (match_operand 4 "") > + (match_operand:RATIO32I 2 "register_operand") > + (match_operand 3 "") > + (match_operand 4 "") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, true); > DONE; > }) > > -(define_expand "len_mask_gather_load" > - [(match_operand:VNX4_QHSD 0 "register_operand") > +(define_expand "len_mask_gather_load" > + [(match_operand:RATIO16 0 "register_operand") > (match_operand 1 "pmode_reg_or_0_operand") > - (match_operand:VNX4_QHSDI 2 "register_operand") > - (match_operand 3 "") > - (match_operand 4 "") > + (match_operand:RATIO16I 2 "register_operand") > + (match_operand 3 "") > + (match_operand 4 "") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, true); > DONE; > }) > > -(define_expand "len_mask_gather_load" > - [(match_operand:VNX8_QHSD 0 "register_operand") > +(define_expand "len_mask_gather_load" > + [(match_operand:RATIO8 0 "register_operand") > (match_operand 1 "pmode_reg_or_0_operand") > - (match_operand:VNX8_QHSDI 2 "register_operand") > - (match_operand 3 "") > - (match_operand 4 "") > + (match_operand:RATIO8I 2 "register_operand") > + (match_operand 3 "") > + (match_operand 4 "") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, true); > DONE; > }) > > -(define_expand "len_mask_gather_load" > - [(match_operand:VNX16_QHSD 0 "register_operand") > +(define_expand "len_mask_gather_load" > + [(match_operand:RATIO4 0 "register_operand") > (match_operand 1 "pmode_reg_or_0_operand") > - (match_operand:VNX16_QHSDI 2 "register_operand") > - (match_operand 3 "") > - (match_operand 4 "") > + (match_operand:RATIO4I 2 "register_operand") > + (match_operand 3 "") > + (match_operand 4 "") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, true); > DONE; > }) > > -(define_expand "len_mask_gather_load" > - [(match_operand:VNX32_QHS 0 "register_operand") > +(define_expand "len_mask_gather_load" > + [(match_operand:RATIO2 0 "register_operand") > (match_operand 1 "pmode_reg_or_0_operand") > - (match_operand:VNX32_QHSI 2 "register_operand") > - (match_operand 3 "") > - (match_operand 4 "") > + (match_operand:RATIO2I 2 "register_operand") > + (match_operand 3 "") > + (match_operand 4 "") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > - "TARGET_VECTOR" > -{ > - riscv_vector::expand_gather_scatter (operands, true); > - DONE; > -}) > - > -(define_expand "len_mask_gather_load" > - [(match_operand:VNX64_QH 0 "register_operand") > - (match_operand 1 "pmode_reg_or_0_operand") > - (match_operand:VNX64_QHI 2 "register_operand") > - (match_operand 3 "") > - (match_operand 4 "") > - (match_operand 5 "autovec_length_operand") > - (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, true); > @@ -170,15 +155,15 @@ > ;; larger SEW. Since RVV indexed load/store support zero extend > ;; implicitly and not support scaling, we should only allow > ;; operands[3] and operands[4] to be const_1_operand. > -(define_expand "len_mask_gather_load" > - [(match_operand:VNX128_Q 0 "register_operand") > +(define_expand "len_mask_gather_load" > + [(match_operand:RATIO1 0 "register_operand") > (match_operand 1 "pmode_reg_or_0_operand") > - (match_operand:VNX128_Q 2 "register_operand") > - (match_operand 3 "const_1_operand") > - (match_operand 4 "const_1_operand") > + (match_operand:RATIO1 2 "register_operand") > + (match_operand 3 "") > + (match_operand 4 "") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, true); > @@ -189,105 +174,90 @@ > ;; =3D=3D Scatter Store > ;; > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > -(define_expand "len_mask_scatter_store" > - [(match_operand 0 "pmode_reg_or_0_operand") > - (match_operand:VNX1_QHSDI 1 "register_operand") > - (match_operand 2 "") > - (match_operand 3 "") > - (match_operand:VNX1_QHSD 4 "register_operand") > - (match_operand 5 "autovec_length_operand") > - (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > - "TARGET_VECTOR" > -{ > - riscv_vector::expand_gather_scatter (operands, false); > - DONE; > -}) > - > -(define_expand "len_mask_scatter_store" > +(define_expand "len_mask_scatter_store" > [(match_operand 0 "pmode_reg_or_0_operand") > - (match_operand:VNX2_QHSDI 1 "register_operand") > - (match_operand 2 "") > - (match_operand 3 "") > - (match_operand:VNX2_QHSD 4 "register_operand") > + (match_operand:RATIO64I 1 "register_operand") > + (match_operand 2 "") > + (match_operand 3 "") > + (match_operand:RATIO64 4 "register_operand") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, false); > DONE; > }) > > -(define_expand "len_mask_scatter_store" > +(define_expand "len_mask_scatter_store" > [(match_operand 0 "pmode_reg_or_0_operand") > - (match_operand:VNX4_QHSDI 1 "register_operand") > - (match_operand 2 "") > - (match_operand 3 "") > - (match_operand:VNX4_QHSD 4 "register_operand") > + (match_operand:RATIO32I 1 "register_operand") > + (match_operand 2 "") > + (match_operand 3 "") > + (match_operand:RATIO32 4 "register_operand") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, false); > DONE; > }) > > -(define_expand "len_mask_scatter_store" > +(define_expand "len_mask_scatter_store" > [(match_operand 0 "pmode_reg_or_0_operand") > - (match_operand:VNX8_QHSDI 1 "register_operand") > - (match_operand 2 "") > - (match_operand 3 "") > - (match_operand:VNX8_QHSD 4 "register_operand") > + (match_operand:RATIO16I 1 "register_operand") > + (match_operand 2 "") > + (match_operand 3 "") > + (match_operand:RATIO16 4 "register_operand") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, false); > DONE; > }) > > -(define_expand "len_mask_scatter_store" > +(define_expand "len_mask_scatter_store" > [(match_operand 0 "pmode_reg_or_0_operand") > - (match_operand:VNX16_QHSDI 1 "register_operand") > - (match_operand 2 "") > - (match_operand 3 "") > - (match_operand:VNX16_QHSD 4 "register_operand") > + (match_operand:RATIO8I 1 "register_operand") > + (match_operand 2 "") > + (match_operand 3 "") > + (match_operand:RATIO8 4 "register_operand") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, false); > DONE; > }) > > -(define_expand "len_mask_scatter_store" > +(define_expand "len_mask_scatter_store" > [(match_operand 0 "pmode_reg_or_0_operand") > - (match_operand:VNX32_QHSI 1 "register_operand") > - (match_operand 2 "") > - (match_operand 3 "") > - (match_operand:VNX32_QHS 4 "register_operand") > + (match_operand:RATIO4I 1 "register_operand") > + (match_operand 2 "") > + (match_operand 3 "") > + (match_operand:RATIO4 4 "register_operand") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, false); > DONE; > }) > > -(define_expand "len_mask_scatter_store" > +(define_expand "len_mask_scatter_store" > [(match_operand 0 "pmode_reg_or_0_operand") > - (match_operand:VNX64_QHI 1 "register_operand") > - (match_operand 2 "") > - (match_operand 3 "") > - (match_operand:VNX64_QH 4 "register_operand") > + (match_operand:RATIO2I 1 "register_operand") > + (match_operand 2 "") > + (match_operand 3 "") > + (match_operand:RATIO2 4 "register_operand") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, false); > @@ -298,15 +268,15 @@ > ;; larger SEW. Since RVV indexed load/store support zero extend > ;; implicitly and not support scaling, we should only allow > ;; operands[3] and operands[4] to be const_1_operand. > -(define_expand "len_mask_scatter_store" > +(define_expand "len_mask_scatter_store" > [(match_operand 0 "pmode_reg_or_0_operand") > - (match_operand:VNX128_Q 1 "register_operand") > - (match_operand 2 "const_1_operand") > - (match_operand 3 "const_1_operand") > - (match_operand:VNX128_Q 4 "register_operand") > + (match_operand:RATIO1 1 "register_operand") > + (match_operand 2 "") > + (match_operand 3 "") > + (match_operand:RATIO1 4 "register_operand") > (match_operand 5 "autovec_length_operand") > (match_operand 6 "const_0_operand") > - (match_operand: 7 "vector_mask_operand")] > + (match_operand: 7 "vector_mask_operand")] > "TARGET_VECTOR" > { > riscv_vector::expand_gather_scatter (operands, false); > diff --git a/gcc/config/riscv/riscv-modes.def > b/gcc/config/riscv/riscv-modes.def > index 1d152709ddc..d6b90e9e304 100644 > --- a/gcc/config/riscv/riscv-modes.def > +++ b/gcc/config/riscv/riscv-modes.def > @@ -27,311 +27,287 @@ FLOAT_MODE (TF, 16, ieee_quad_format); > /* Encode the ratio of SEW/LMUL into the mask types. There are the > following > * mask types. */ > > -/* | Mode | MIN_VLEN =3D 32 | MIN_VLEN =3D 64 | MIN_VLEN =3D 128 | > - | | SEW/LMUL | SEW/LMUL | SEW/LMUL | > - | VNx1BI | 32 | 64 | 128 | > - | VNx2BI | 16 | 32 | 64 | > - | VNx4BI | 8 | 16 | 32 | > - | VNx8BI | 4 | 8 | 16 | > - | VNx16BI | 2 | 4 | 8 | > - | VNx32BI | 1 | 2 | 4 | > - | VNx64BI | N/A | 1 | 2 | > - | VNx128BI | N/A | N/A | 1 | */ > +/* Encode the ratio of SEW/LMUL into the mask types. > + There are the following mask types. > + > + n =3D SEW/LMUL > + > + |Modes| n =3D 1 | n =3D 2 | n =3D 4 | n =3D 8 | n =3D 16 | n =3D 32 | = n =3D 64 | > + |BI |RVVM1BI |RVVMF2BI |RVVMF4BI |RVVMF8BI |RVVMF16BI |RVVMF32BI > |RVVMF64BI | */ > > /* For RVV modes, each boolean value occupies 1-bit. > 4th argument is specify the minmial possible size of the vector mode, > and will adjust to the right size by ADJUST_BYTESIZE. */ > -VECTOR_BOOL_MODE (VNx1BI, 1, BI, 1); > -VECTOR_BOOL_MODE (VNx2BI, 2, BI, 1); > -VECTOR_BOOL_MODE (VNx4BI, 4, BI, 1); > -VECTOR_BOOL_MODE (VNx8BI, 8, BI, 1); > -VECTOR_BOOL_MODE (VNx16BI, 16, BI, 2); > -VECTOR_BOOL_MODE (VNx32BI, 32, BI, 4); > -VECTOR_BOOL_MODE (VNx64BI, 64, BI, 8); > -VECTOR_BOOL_MODE (VNx128BI, 128, BI, 16); > - > -ADJUST_NUNITS (VNx1BI, riscv_v_adjust_nunits (VNx1BImode, 1)); > -ADJUST_NUNITS (VNx2BI, riscv_v_adjust_nunits (VNx2BImode, 2)); > -ADJUST_NUNITS (VNx4BI, riscv_v_adjust_nunits (VNx4BImode, 4)); > -ADJUST_NUNITS (VNx8BI, riscv_v_adjust_nunits (VNx8BImode, 8)); > -ADJUST_NUNITS (VNx16BI, riscv_v_adjust_nunits (VNx16BImode, 16)); > -ADJUST_NUNITS (VNx32BI, riscv_v_adjust_nunits (VNx32BImode, 32)); > -ADJUST_NUNITS (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 64)); > -ADJUST_NUNITS (VNx128BI, riscv_v_adjust_nunits (VNx128BImode, 128)); > - > -ADJUST_ALIGNMENT (VNx1BI, 1); > -ADJUST_ALIGNMENT (VNx2BI, 1); > -ADJUST_ALIGNMENT (VNx4BI, 1); > -ADJUST_ALIGNMENT (VNx8BI, 1); > -ADJUST_ALIGNMENT (VNx16BI, 1); > -ADJUST_ALIGNMENT (VNx32BI, 1); > -ADJUST_ALIGNMENT (VNx64BI, 1); > -ADJUST_ALIGNMENT (VNx128BI, 1); > - > -ADJUST_BYTESIZE (VNx1BI, riscv_v_adjust_bytesize (VNx1BImode, 1)); > -ADJUST_BYTESIZE (VNx2BI, riscv_v_adjust_bytesize (VNx2BImode, 1)); > -ADJUST_BYTESIZE (VNx4BI, riscv_v_adjust_bytesize (VNx4BImode, 1)); > -ADJUST_BYTESIZE (VNx8BI, riscv_v_adjust_bytesize (VNx8BImode, 1)); > -ADJUST_BYTESIZE (VNx16BI, riscv_v_adjust_bytesize (VNx16BImode, 2)); > -ADJUST_BYTESIZE (VNx32BI, riscv_v_adjust_bytesize (VNx32BImode, 4)); > -ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_bytesize (VNx64BImode, 8)); > -ADJUST_BYTESIZE (VNx128BI, riscv_v_adjust_bytesize (VNx128BImode, 16)); > - > -ADJUST_PRECISION (VNx1BI, riscv_v_adjust_precision (VNx1BImode, 1)); > -ADJUST_PRECISION (VNx2BI, riscv_v_adjust_precision (VNx2BImode, 2)); > -ADJUST_PRECISION (VNx4BI, riscv_v_adjust_precision (VNx4BImode, 4)); > -ADJUST_PRECISION (VNx8BI, riscv_v_adjust_precision (VNx8BImode, 8)); > -ADJUST_PRECISION (VNx16BI, riscv_v_adjust_precision (VNx16BImode, 16)); > -ADJUST_PRECISION (VNx32BI, riscv_v_adjust_precision (VNx32BImode, 32)); > -ADJUST_PRECISION (VNx64BI, riscv_v_adjust_precision (VNx64BImode, 64)); > -ADJUST_PRECISION (VNx128BI, riscv_v_adjust_precision (VNx128BImode, 128)= ); > - > -/* > - | Mode | MIN_VLEN=3D32 | MIN_VLEN=3D32 | MIN_VLEN=3D64 | MIN_V= LEN=3D64 > | MIN_VLEN=3D128 | MIN_VLEN=3D128 | > - | | LMUL | SEW/LMUL | LMUL | SEW/LMUL > | LMUL | SEW/LMUL | > - | VNx1QI | MF4 | 32 | MF8 | 64 > | N/A | N/A | > - | VNx2QI | MF2 | 16 | MF4 | 32 > | MF8 | 64 | > - | VNx4QI | M1 | 8 | MF2 | 16 > | MF4 | 32 | > - | VNx8QI | M2 | 4 | M1 | 8 > | MF2 | 16 | > - | VNx16QI | M4 | 2 | M2 | 4 > | M1 | 8 | > - | VNx32QI | M8 | 1 | M4 | 2 > | M2 | 4 | > - | VNx64QI | N/A | N/A | M8 | 1 > | M4 | 2 | > - | VNx128QI | N/A | N/A | N/A | N/A > | M8 | 1 | > - | VNx1(HI|HF) | MF2 | 32 | MF4 | 64 > | N/A | N/A | > - | VNx2(HI|HF) | M1 | 16 | MF2 | 32 > | MF4 | 64 | > - | VNx4(HI|HF) | M2 | 8 | M1 | 16 > | MF2 | 32 | > - | VNx8(HI|HF) | M4 | 4 | M2 | 8 > | M1 | 16 | > - | VNx16(HI|HF)| M8 | 2 | M4 | 4 > | M2 | 8 | > - | VNx32(HI|HF)| N/A | N/A | M8 | 2 > | M4 | 4 | > - | VNx64(HI|HF)| N/A | N/A | N/A | N/A > | M8 | 2 | > - | VNx1(SI|SF) | M1 | 32 | MF2 | 64 > | MF2 | 64 | > - | VNx2(SI|SF) | M2 | 16 | M1 | 32 > | M1 | 32 | > - | VNx4(SI|SF) | M4 | 8 | M2 | 16 > | M2 | 16 | > - | VNx8(SI|SF) | M8 | 4 | M4 | 8 > | M4 | 8 | > - | VNx16(SI|SF)| N/A | N/A | M8 | 4 > | M8 | 4 | > - | VNx1(DI|DF) | N/A | N/A | M1 | 64 > | N/A | N/A | > - | VNx2(DI|DF) | N/A | N/A | M2 | 32 > | M1 | 64 | > - | VNx4(DI|DF) | N/A | N/A | M4 | 16 > | M2 | 32 | > - | VNx8(DI|DF) | N/A | N/A | M8 | 8 > | M4 | 16 | > - | VNx16(DI|DF)| N/A | N/A | N/A | N/A > | M8 | 8 | > -*/ > - > -/* Define RVV modes whose sizes are multiples of 64-bit chunks. */ > -#define RVV_MODES(NVECS, VB, VH, VS, VD) > \ > - VECTOR_MODE_WITH_PREFIX (VNx, INT, QI, 8 * NVECS, 0); > \ > - VECTOR_MODE_WITH_PREFIX (VNx, INT, HI, 4 * NVECS, 0); > \ > - VECTOR_MODE_WITH_PREFIX (VNx, FLOAT, HF, 4 * NVECS, 0); > \ > - VECTOR_MODE_WITH_PREFIX (VNx, INT, SI, 2 * NVECS, 0); > \ > - VECTOR_MODE_WITH_PREFIX (VNx, FLOAT, SF, 2 * NVECS, 0); > \ > - VECTOR_MODE_WITH_PREFIX (VNx, INT, DI, NVECS, 0); > \ > - VECTOR_MODE_WITH_PREFIX (VNx, FLOAT, DF, NVECS, 0); > \ > +VECTOR_BOOL_MODE (RVVM1BI, 64, BI, 8); > +VECTOR_BOOL_MODE (RVVMF2BI, 32, BI, 4); > +VECTOR_BOOL_MODE (RVVMF4BI, 16, BI, 2); > +VECTOR_BOOL_MODE (RVVMF8BI, 8, BI, 1); > +VECTOR_BOOL_MODE (RVVMF16BI, 4, BI, 1); > +VECTOR_BOOL_MODE (RVVMF32BI, 2, BI, 1); > +VECTOR_BOOL_MODE (RVVMF64BI, 1, BI, 1); > + > +ADJUST_NUNITS (RVVM1BI, riscv_v_adjust_nunits (RVVM1BImode, 64)); > +ADJUST_NUNITS (RVVMF2BI, riscv_v_adjust_nunits (RVVMF2BImode, 32)); > +ADJUST_NUNITS (RVVMF4BI, riscv_v_adjust_nunits (RVVMF4BImode, 16)); > +ADJUST_NUNITS (RVVMF8BI, riscv_v_adjust_nunits (RVVMF8BImode, 8)); > +ADJUST_NUNITS (RVVMF16BI, riscv_v_adjust_nunits (RVVMF16BImode, 4)); > +ADJUST_NUNITS (RVVMF32BI, riscv_v_adjust_nunits (RVVMF32BImode, 2)); > +ADJUST_NUNITS (RVVMF64BI, riscv_v_adjust_nunits (RVVMF64BImode, 1)); > + > +ADJUST_ALIGNMENT (RVVM1BI, 1); > +ADJUST_ALIGNMENT (RVVMF2BI, 1); > +ADJUST_ALIGNMENT (RVVMF4BI, 1); > +ADJUST_ALIGNMENT (RVVMF8BI, 1); > +ADJUST_ALIGNMENT (RVVMF16BI, 1); > +ADJUST_ALIGNMENT (RVVMF32BI, 1); > +ADJUST_ALIGNMENT (RVVMF64BI, 1); > + > +ADJUST_PRECISION (RVVM1BI, riscv_v_adjust_precision (RVVM1BImode, 64)); > +ADJUST_PRECISION (RVVMF2BI, riscv_v_adjust_precision (RVVMF2BImode, 32)); > +ADJUST_PRECISION (RVVMF4BI, riscv_v_adjust_precision (RVVMF4BImode, 16)); > +ADJUST_PRECISION (RVVMF8BI, riscv_v_adjust_precision (RVVMF8BImode, 8)); > +ADJUST_PRECISION (RVVMF16BI, riscv_v_adjust_precision (RVVMF16BImode, 4)= ); > +ADJUST_PRECISION (RVVMF32BI, riscv_v_adjust_precision (RVVMF32BImode, 2)= ); > +ADJUST_PRECISION (RVVMF64BI, riscv_v_adjust_precision (RVVMF64BImode, 1)= ); > + > +ADJUST_BYTESIZE (RVVM1BI, riscv_v_adjust_bytesize (RVVM1BImode, 8)); > +ADJUST_BYTESIZE (RVVMF2BI, riscv_v_adjust_bytesize (RVVMF2BImode, 4)); > +ADJUST_BYTESIZE (RVVMF4BI, riscv_v_adjust_bytesize (RVVMF4BImode, 2)); > +ADJUST_BYTESIZE (RVVMF8BI, riscv_v_adjust_bytesize (RVVMF8BImode, 1)); > +ADJUST_BYTESIZE (RVVMF16BI, riscv_v_adjust_bytesize (RVVMF16BImode, 1)); > +ADJUST_BYTESIZE (RVVMF32BI, riscv_v_adjust_bytesize (RVVMF32BImode, 1)); > +ADJUST_BYTESIZE (RVVMF64BI, riscv_v_adjust_bytesize (RVVMF64BImode, 1)); > + > +/* Encode SEW and LMUL into data types. > + We enforce the constraint LMUL =E2=89=A5 SEW/ELEN in the implementati= on. > + There are the following data types for ELEN =3D 64. > + > + |Modes|LMUL=3D1 |LMUL=3D2 |LMUL=3D4 |LMUL=3D8 |LMUL=3D1/2|LMUL=3D1/4|= LMUL=3D1/8| > + |DI |RVVM1DI|RVVM2DI|RVVM4DI|RVVM8DI|N/A |N/A |N/A | > + |SI |RVVM1SI|RVVM2SI|RVVM4SI|RVVM8SI|RVVMF2SI|N/A |N/A | > + |HI |RVVM1HI|RVVM2HI|RVVM4HI|RVVM8HI|RVVMF2HI|RVVMF4HI|N/A | > + |QI |RVVM1QI|RVVM2QI|RVVM4QI|RVVM8QI|RVVMF2QI|RVVMF4QI|RVVMF8QI| > + |DF |RVVM1DF|RVVM2DF|RVVM4DF|RVVM8DF|N/A |N/A |N/A | > + |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|RVVMF2SF|N/A |N/A | > + |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|RVVMF4HF|N/A | > + > +There are the following data types for ELEN =3D 32. > + > + |Modes|LMUL=3D1 |LMUL=3D2 |LMUL=3D4 |LMUL=3D8 |LMUL=3D1/2|LMUL=3D1/4|= LMUL=3D1/8| > + |SI |RVVM1SI|RVVM2SI|RVVM4SI|RVVM8SI|N/A |N/A |N/A | > + |HI |RVVM1HI|RVVM2HI|RVVM4HI|RVVM8HI|RVVMF2HI|N/A |N/A | > + |QI |RVVM1QI|RVVM2QI|RVVM4QI|RVVM8QI|RVVMF2QI|RVVMF4QI|N/A | > + |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|N/A |N/A |N/A | > + |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|N/A |N/A | */ > + > +#define RVV_WHOLE_MODES(LMUL) > \ > + VECTOR_MODE_WITH_PREFIX (RVVM, INT, QI, LMUL, 0); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM, INT, HI, LMUL, 0); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, HF, LMUL, 0); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM, INT, SI, LMUL, 0); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, SF, LMUL, 0); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM, INT, DI, LMUL, 0); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, DF, LMUL, 0); > \ > + > \ > + ADJUST_NUNITS (RVVM##LMUL##QI, > \ > + riscv_v_adjust_nunits (RVVM##LMUL##QImode, false, LMUL, > 1)); \ > + ADJUST_NUNITS (RVVM##LMUL##HI, > \ > + riscv_v_adjust_nunits (RVVM##LMUL##HImode, false, LMUL, > 1)); \ > + ADJUST_NUNITS (RVVM##LMUL##SI, > \ > + riscv_v_adjust_nunits (RVVM##LMUL##SImode, false, LMUL, > 1)); \ > + ADJUST_NUNITS (RVVM##LMUL##DI, > \ > + riscv_v_adjust_nunits (RVVM##LMUL##DImode, false, LMUL, > 1)); \ > + ADJUST_NUNITS (RVVM##LMUL##HF, > \ > + riscv_v_adjust_nunits (RVVM##LMUL##HFmode, false, LMUL, > 1)); \ > + ADJUST_NUNITS (RVVM##LMUL##SF, > \ > + riscv_v_adjust_nunits (RVVM##LMUL##SFmode, false, LMUL, > 1)); \ > + ADJUST_NUNITS (RVVM##LMUL##DF, > \ > + riscv_v_adjust_nunits (RVVM##LMUL##DFmode, false, LMUL, > 1)); \ > + > \ > + ADJUST_ALIGNMENT (RVVM##LMUL##QI, 1); > \ > + ADJUST_ALIGNMENT (RVVM##LMUL##HI, 2); > \ > + ADJUST_ALIGNMENT (RVVM##LMUL##SI, 4); > \ > + ADJUST_ALIGNMENT (RVVM##LMUL##DI, 8); > \ > + ADJUST_ALIGNMENT (RVVM##LMUL##HF, 2); > \ > + ADJUST_ALIGNMENT (RVVM##LMUL##SF, 4); > \ > + ADJUST_ALIGNMENT (RVVM##LMUL##DF, 8); > + > +RVV_WHOLE_MODES (1) > +RVV_WHOLE_MODES (2) > +RVV_WHOLE_MODES (4) > +RVV_WHOLE_MODES (8) > + > +#define RVV_FRACT_MODE(TYPE, MODE, LMUL, ALIGN) > \ > + VECTOR_MODE_WITH_PREFIX (RVVMF, TYPE, MODE, LMUL, 0); > \ > + ADJUST_NUNITS (RVVMF##LMUL##MODE, > \ > + riscv_v_adjust_nunits (RVVMF##LMUL##MODE##mode, true, > LMUL, \ > + 1)); > \ > + > \ > + ADJUST_ALIGNMENT (RVVMF##LMUL##MODE, ALIGN); > + > +RVV_FRACT_MODE (INT, QI, 2, 1) > +RVV_FRACT_MODE (INT, QI, 4, 1) > +RVV_FRACT_MODE (INT, QI, 8, 1) > +RVV_FRACT_MODE (INT, HI, 2, 2) > +RVV_FRACT_MODE (INT, HI, 4, 2) > +RVV_FRACT_MODE (FLOAT, HF, 2, 2) > +RVV_FRACT_MODE (FLOAT, HF, 4, 2) > +RVV_FRACT_MODE (INT, SI, 2, 4) > +RVV_FRACT_MODE (FLOAT, SF, 2, 4) > + > +/* Tuple modes for segment loads/stores according to NF. > + > + Tuple modes format: RVVx > + > + When LMUL is MF8/MF4/MF2/M1, NF can be 2 ~ 8. > + When LMUL is M2, NF can be 2 ~ 4. > + When LMUL is M4, NF can be 4. */ > + > +#define RVV_NF8_MODES(NF) > \ > + VECTOR_MODE_WITH_PREFIX (RVVMF8x, INT, QI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVMF4x, INT, QI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVMF2x, INT, QI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM1x, INT, QI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVMF4x, INT, HI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVMF2x, INT, HI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM1x, INT, HI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVMF4x, FLOAT, HF, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVMF2x, FLOAT, HF, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM1x, FLOAT, HF, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVMF2x, INT, SI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM1x, INT, SI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVMF2x, FLOAT, SF, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM1x, FLOAT, SF, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM1x, INT, DI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM1x, FLOAT, DF, NF, 1); > \ > + > \ > + ADJUST_NUNITS (RVVMF8x##NF##QI, > \ > + riscv_v_adjust_nunits (RVVMF8x##NF##QImode, true, 8, > NF)); \ > + ADJUST_NUNITS (RVVMF4x##NF##QI, > \ > + riscv_v_adjust_nunits (RVVMF4x##NF##QImode, true, 4, > NF)); \ > + ADJUST_NUNITS (RVVMF2x##NF##QI, > \ > + riscv_v_adjust_nunits (RVVMF2x##NF##QImode, true, 2, > NF)); \ > + ADJUST_NUNITS (RVVM1x##NF##QI, > \ > + riscv_v_adjust_nunits (RVVM1x##NF##QImode, false, 1, > NF)); \ > + ADJUST_NUNITS (RVVMF4x##NF##HI, > \ > + riscv_v_adjust_nunits (RVVMF4x##NF##HImode, true, 4, > NF)); \ > + ADJUST_NUNITS (RVVMF2x##NF##HI, > \ > + riscv_v_adjust_nunits (RVVMF2x##NF##HImode, true, 2, > NF)); \ > + ADJUST_NUNITS (RVVM1x##NF##HI, > \ > + riscv_v_adjust_nunits (RVVM1x##NF##HImode, false, 1, > NF)); \ > + ADJUST_NUNITS (RVVMF4x##NF##HF, > \ > + riscv_v_adjust_nunits (RVVMF4x##NF##HFmode, true, 4, > NF)); \ > + ADJUST_NUNITS (RVVMF2x##NF##HF, > \ > + riscv_v_adjust_nunits (RVVMF2x##NF##HFmode, true, 2, > NF)); \ > + ADJUST_NUNITS (RVVM1x##NF##HF, > \ > + riscv_v_adjust_nunits (RVVM1x##NF##HFmode, false, 1, > NF)); \ > + ADJUST_NUNITS (RVVMF2x##NF##SI, > \ > + riscv_v_adjust_nunits (RVVMF2x##NF##SImode, true, 2, > NF)); \ > + ADJUST_NUNITS (RVVM1x##NF##SI, > \ > + riscv_v_adjust_nunits (RVVM1x##NF##SImode, false, 1, > NF)); \ > + ADJUST_NUNITS (RVVMF2x##NF##SF, > \ > + riscv_v_adjust_nunits (RVVMF2x##NF##SFmode, true, 2, > NF)); \ > + ADJUST_NUNITS (RVVM1x##NF##SF, > \ > + riscv_v_adjust_nunits (RVVM1x##NF##SFmode, false, 1, > NF)); \ > + ADJUST_NUNITS (RVVM1x##NF##DI, > \ > + riscv_v_adjust_nunits (RVVM1x##NF##DImode, false, 1, > NF)); \ > + ADJUST_NUNITS (RVVM1x##NF##DF, > \ > + riscv_v_adjust_nunits (RVVM1x##NF##DFmode, false, 1, > NF)); \ > + > \ > + ADJUST_ALIGNMENT (RVVMF8x##NF##QI, 1); > \ > + ADJUST_ALIGNMENT (RVVMF4x##NF##QI, 1); > \ > + ADJUST_ALIGNMENT (RVVMF2x##NF##QI, 1); > \ > + ADJUST_ALIGNMENT (RVVM1x##NF##QI, 1); > \ > + ADJUST_ALIGNMENT (RVVMF4x##NF##HI, 2); > \ > + ADJUST_ALIGNMENT (RVVMF2x##NF##HI, 2); > \ > + ADJUST_ALIGNMENT (RVVM1x##NF##HI, 2); > \ > + ADJUST_ALIGNMENT (RVVMF4x##NF##HF, 2); > \ > + ADJUST_ALIGNMENT (RVVMF2x##NF##HF, 2); > \ > + ADJUST_ALIGNMENT (RVVM1x##NF##HF, 2); > \ > + ADJUST_ALIGNMENT (RVVMF2x##NF##SI, 4); > \ > + ADJUST_ALIGNMENT (RVVM1x##NF##SI, 4); > \ > + ADJUST_ALIGNMENT (RVVMF2x##NF##SF, 4); > \ > + ADJUST_ALIGNMENT (RVVM1x##NF##SF, 4); > \ > + ADJUST_ALIGNMENT (RVVM1x##NF##DI, 8); > \ > + ADJUST_ALIGNMENT (RVVM1x##NF##DF, 8); > + > +RVV_NF8_MODES (8) > +RVV_NF8_MODES (7) > +RVV_NF8_MODES (6) > +RVV_NF8_MODES (5) > +RVV_NF8_MODES (4) > +RVV_NF8_MODES (3) > +RVV_NF8_MODES (2) > + > +#define RVV_NF4_MODES(NF) > \ > + VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, QI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, HI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, HF, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, SI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, SF, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, DI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, DF, NF, 1); > \ > > \ > - ADJUST_NUNITS (VB##QI, riscv_v_adjust_nunits (VB##QI##mode, NVECS * > 8)); \ > - ADJUST_NUNITS (VH##HI, riscv_v_adjust_nunits (VH##HI##mode, NVECS * > 4)); \ > - ADJUST_NUNITS (VS##SI, riscv_v_adjust_nunits (VS##SI##mode, NVECS * > 2)); \ > - ADJUST_NUNITS (VD##DI, riscv_v_adjust_nunits (VD##DI##mode, NVECS)); > \ > - ADJUST_NUNITS (VH##HF, riscv_v_adjust_nunits (VH##HF##mode, NVECS * > 4)); \ > - ADJUST_NUNITS (VS##SF, riscv_v_adjust_nunits (VS##SF##mode, NVECS * > 2)); \ > - ADJUST_NUNITS (VD##DF, riscv_v_adjust_nunits (VD##DF##mode, NVECS)); > \ > + ADJUST_NUNITS (RVVM2x##NF##QI, > \ > + riscv_v_adjust_nunits (RVVM2x##NF##QImode, false, 2, > NF)); \ > + ADJUST_NUNITS (RVVM2x##NF##HI, > \ > + riscv_v_adjust_nunits (RVVM2x##NF##HImode, false, 2, > NF)); \ > + ADJUST_NUNITS (RVVM2x##NF##HF, > \ > + riscv_v_adjust_nunits (RVVM2x##NF##HFmode, false, 2, > NF)); \ > + ADJUST_NUNITS (RVVM2x##NF##SI, > \ > + riscv_v_adjust_nunits (RVVM2x##NF##SImode, false, 2, > NF)); \ > + ADJUST_NUNITS (RVVM2x##NF##SF, > \ > + riscv_v_adjust_nunits (RVVM2x##NF##SFmode, false, 2, > NF)); \ > + ADJUST_NUNITS (RVVM2x##NF##DI, > \ > + riscv_v_adjust_nunits (RVVM2x##NF##DImode, false, 2, > NF)); \ > + ADJUST_NUNITS (RVVM2x##NF##DF, > \ > + riscv_v_adjust_nunits (RVVM2x##NF##DFmode, false, 2, > NF)); \ > > \ > - ADJUST_ALIGNMENT (VB##QI, 1); > \ > - ADJUST_ALIGNMENT (VH##HI, 2); > \ > - ADJUST_ALIGNMENT (VS##SI, 4); > \ > - ADJUST_ALIGNMENT (VD##DI, 8); > \ > - ADJUST_ALIGNMENT (VH##HF, 2); > \ > - ADJUST_ALIGNMENT (VS##SF, 4); > \ > - ADJUST_ALIGNMENT (VD##DF, 8); > - > -RVV_MODES (1, VNx8, VNx4, VNx2, VNx1) > -RVV_MODES (2, VNx16, VNx8, VNx4, VNx2) > -RVV_MODES (4, VNx32, VNx16, VNx8, VNx4) > -RVV_MODES (8, VNx64, VNx32, VNx16, VNx8) > -RVV_MODES (16, VNx128, VNx64, VNx32, VNx16) > - > -VECTOR_MODES_WITH_PREFIX (VNx, INT, 4, 0); > -VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 4, 0); > -ADJUST_NUNITS (VNx4QI, riscv_v_adjust_nunits (VNx4QImode, 4)); > -ADJUST_NUNITS (VNx2HI, riscv_v_adjust_nunits (VNx2HImode, 2)); > -ADJUST_NUNITS (VNx2HF, riscv_v_adjust_nunits (VNx2HFmode, 2)); > -ADJUST_ALIGNMENT (VNx4QI, 1); > -ADJUST_ALIGNMENT (VNx2HI, 2); > -ADJUST_ALIGNMENT (VNx2HF, 2); > - > -/* 'VECTOR_MODES_WITH_PREFIX' does not allow ncomponents < 2. > - So we use 'VECTOR_MODE_WITH_PREFIX' to define VNx1SImode and > VNx1SFmode. */ > -VECTOR_MODE_WITH_PREFIX (VNx, INT, SI, 1, 0); > -VECTOR_MODE_WITH_PREFIX (VNx, FLOAT, SF, 1, 0); > -ADJUST_NUNITS (VNx1SI, riscv_v_adjust_nunits (VNx1SImode, 1)); > -ADJUST_NUNITS (VNx1SF, riscv_v_adjust_nunits (VNx1SFmode, 1)); > -ADJUST_ALIGNMENT (VNx1SI, 4); > -ADJUST_ALIGNMENT (VNx1SF, 4); > - > -VECTOR_MODES_WITH_PREFIX (VNx, INT, 2, 0); > -ADJUST_NUNITS (VNx2QI, riscv_v_adjust_nunits (VNx2QImode, 2)); > -ADJUST_ALIGNMENT (VNx2QI, 1); > - > -/* 'VECTOR_MODES_WITH_PREFIX' does not allow ncomponents < 2. > - So we use 'VECTOR_MODE_WITH_PREFIX' to define VNx1HImode and > VNx1HFmode. */ > -VECTOR_MODE_WITH_PREFIX (VNx, INT, HI, 1, 0); > -VECTOR_MODE_WITH_PREFIX (VNx, FLOAT, HF, 1, 0); > -ADJUST_NUNITS (VNx1HI, riscv_v_adjust_nunits (VNx1HImode, 1)); > -ADJUST_NUNITS (VNx1HF, riscv_v_adjust_nunits (VNx1HFmode, 1)); > -ADJUST_ALIGNMENT (VNx1HI, 2); > -ADJUST_ALIGNMENT (VNx1HF, 2); > - > -/* 'VECTOR_MODES_WITH_PREFIX' does not allow ncomponents < 2. > - So we use 'VECTOR_MODE_WITH_PREFIX' to define VNx1QImode. */ > -VECTOR_MODE_WITH_PREFIX (VNx, INT, QI, 1, 0); > -ADJUST_NUNITS (VNx1QI, riscv_v_adjust_nunits (VNx1QImode, 1)); > -ADJUST_ALIGNMENT (VNx1QI, 1); > - > -/* Tuple modes for segment loads/stores according to NF, NF value can be > 2 ~ 8. */ > - > -/* > - | Mode | MIN_VLEN=3D32 | MIN_VLEN=3D32 | MIN_VLEN=3D64 | > MIN_VLEN=3D64 | MIN_VLEN=3D128 | MIN_VLEN=3D128 | > - | | LMUL | SEW/LMUL | LMUL | SEW/LMUL > | LMUL | SEW/LMUL | > - | VNxNFx1QI | MF4 | 32 | MF8 | 64 > | N/A | N/A | > - | VNxNFx2QI | MF2 | 16 | MF4 | 32 > | MF8 | 64 | > - | VNxNFx4QI | M1 | 8 | MF2 | 16 > | MF4 | 32 | > - | VNxNFx8QI | M2 | 4 | M1 | 8 > | MF2 | 16 | > - | VNxNFx16QI | M4 | 2 | M2 | 4 > | M1 | 8 | > - | VNxNFx32QI | M8 | 1 | M4 | 2 > | M2 | 4 | > - | VNxNFx64QI | N/A | N/A | M8 | 1 > | M4 | 2 | > - | VNxNFx128QI | N/A | N/A | N/A | N/A > | M8 | 1 | > - | VNxNFx1(HI|HF) | MF2 | 32 | MF4 | 64 > | N/A | N/A | > - | VNxNFx2(HI|HF) | M1 | 16 | MF2 | 32 > | MF4 | 64 | > - | VNxNFx4(HI|HF) | M2 | 8 | M1 | 16 > | MF2 | 32 | > - | VNxNFx8(HI|HF) | M4 | 4 | M2 | 8 > | M1 | 16 | > - | VNxNFx16(HI|HF)| M8 | 2 | M4 | 4 > | M2 | 8 | > - | VNxNFx32(HI|HF)| N/A | N/A | M8 | 2 > | M4 | 4 | > - | VNxNFx64(HI|HF)| N/A | N/A | N/A | N/A > | M8 | 2 | > - | VNxNFx1(SI|SF) | M1 | 32 | MF2 | 64 > | MF2 | 64 | > - | VNxNFx2(SI|SF) | M2 | 16 | M1 | 32 > | M1 | 32 | > - | VNxNFx4(SI|SF) | M4 | 8 | M2 | 16 > | M2 | 16 | > - | VNxNFx8(SI|SF) | M8 | 4 | M4 | 8 > | M4 | 8 | > - | VNxNFx16(SI|SF)| N/A | N/A | M8 | 4 > | M8 | 4 | > - | VNxNFx1(DI|DF) | N/A | N/A | M1 | 64 > | N/A | N/A | > - | VNxNFx2(DI|DF) | N/A | N/A | M2 | 32 > | M1 | 64 | > - | VNxNFx4(DI|DF) | N/A | N/A | M4 | 16 > | M2 | 32 | > - | VNxNFx8(DI|DF) | N/A | N/A | M8 | 8 > | M4 | 16 | > - | VNxNFx16(DI|DF)| N/A | N/A | N/A | N/A > | M8 | 8 | > -*/ > - > -#define RVV_TUPLE_MODES(NBYTES, NSUBPARTS, VB, VH, VS, VD) > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, NBYTES, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, NBYTES / 2, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, HF, NBYTES / 2, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, SI, NBYTES / 4, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, SF, NBYTES / 4, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, DI, NBYTES / 8, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, DF, NBYTES / 8, 1); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x##VB##QI, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VB##QI##mode, > \ > - VB * NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x##VH##HI, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VH##HI##mode, > \ > - VH * NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x##VS##SI, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VS##SI##mode, > \ > - VS * NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x##VD##DI, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VD##DI##mode, > \ > - VD * NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x##VH##HF, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VH##HF##mode, > \ > - VH * NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x##VS##SF, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VS##SF##mode, > \ > - VS * NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x##VD##DF, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VD##DF##mode, > \ > - VD * NSUBPARTS)); > \ > + ADJUST_ALIGNMENT (RVVM2x##NF##QI, 1); > \ > + ADJUST_ALIGNMENT (RVVM2x##NF##HI, 2); > \ > + ADJUST_ALIGNMENT (RVVM2x##NF##HF, 2); > \ > + ADJUST_ALIGNMENT (RVVM2x##NF##SI, 4); > \ > + ADJUST_ALIGNMENT (RVVM2x##NF##SF, 4); > \ > + ADJUST_ALIGNMENT (RVVM2x##NF##DI, 8); > \ > + ADJUST_ALIGNMENT (RVVM2x##NF##DF, 8); > + > +RVV_NF4_MODES (2) > +RVV_NF4_MODES (3) > +RVV_NF4_MODES (4) > + > +#define RVV_NF2_MODES(NF) > \ > + VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, QI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, HI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, HF, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, SI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, SF, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, DI, NF, 1); > \ > + VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, DF, NF, 1); > \ > > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VB##QI, 1); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VH##HI, 2); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VS##SI, 4); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VD##DI, 8); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VH##HF, 2); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VS##SF, 4); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VD##DF, 8); > - > -RVV_TUPLE_MODES (8, 2, 8, 4, 2, 1) > -RVV_TUPLE_MODES (8, 3, 8, 4, 2, 1) > -RVV_TUPLE_MODES (8, 4, 8, 4, 2, 1) > -RVV_TUPLE_MODES (8, 5, 8, 4, 2, 1) > -RVV_TUPLE_MODES (8, 6, 8, 4, 2, 1) > -RVV_TUPLE_MODES (8, 7, 8, 4, 2, 1) > -RVV_TUPLE_MODES (8, 8, 8, 4, 2, 1) > - > -RVV_TUPLE_MODES (16, 2, 16, 8, 4, 2) > -RVV_TUPLE_MODES (16, 3, 16, 8, 4, 2) > -RVV_TUPLE_MODES (16, 4, 16, 8, 4, 2) > -RVV_TUPLE_MODES (16, 5, 16, 8, 4, 2) > -RVV_TUPLE_MODES (16, 6, 16, 8, 4, 2) > -RVV_TUPLE_MODES (16, 7, 16, 8, 4, 2) > -RVV_TUPLE_MODES (16, 8, 16, 8, 4, 2) > - > -RVV_TUPLE_MODES (32, 2, 32, 16, 8, 4) > -RVV_TUPLE_MODES (32, 3, 32, 16, 8, 4) > -RVV_TUPLE_MODES (32, 4, 32, 16, 8, 4) > - > -RVV_TUPLE_MODES (64, 2, 64, 32, 16, 8) > - > -#define RVV_TUPLE_PARTIAL_MODES(NSUBPARTS) > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, 1, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, 1, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, HF, 1, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, SI, 1, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, SF, 1, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, 2, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, 2, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, HF, 2, 1); > \ > - VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, 4, 1); > \ > + ADJUST_NUNITS (RVVM4x##NF##QI, > \ > + riscv_v_adjust_nunits (RVVM4x##NF##QImode, false, 4, > NF)); \ > + ADJUST_NUNITS (RVVM4x##NF##HI, > \ > + riscv_v_adjust_nunits (RVVM4x##NF##HImode, false, 4, > NF)); \ > + ADJUST_NUNITS (RVVM4x##NF##HF, > \ > + riscv_v_adjust_nunits (RVVM4x##NF##HFmode, false, 4, > NF)); \ > + ADJUST_NUNITS (RVVM4x##NF##SI, > \ > + riscv_v_adjust_nunits (RVVM4x##NF##SImode, false, 4, > NF)); \ > + ADJUST_NUNITS (RVVM4x##NF##SF, > \ > + riscv_v_adjust_nunits (RVVM4x##NF##SFmode, false, 4, > NF)); \ > + ADJUST_NUNITS (RVVM4x##NF##DI, > \ > + riscv_v_adjust_nunits (RVVM4x##NF##DImode, false, 4, > NF)); \ > + ADJUST_NUNITS (RVVM4x##NF##DF, > \ > + riscv_v_adjust_nunits (RVVM4x##NF##DFmode, false, 4, > NF)); \ > > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x1QI, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x1QI##mode, > \ > - NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x1HI, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x1HI##mode, > \ > - NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x1HF, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x1HF##mode, > \ > - NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x1SI, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x1SI##mode, > \ > - NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x1SF, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x1SF##mode, > \ > - NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x2QI, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x2QI##mode, > \ > - 2 * NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x2HI, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x2HI##mode, > \ > - 2 * NSUBPARTS)); > \ > -ADJUST_NUNITS (VNx##NSUBPARTS##x2HF, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x2HF##mode, > \ > - 2 * NSUBPARTS)); > \ > - ADJUST_NUNITS (VNx##NSUBPARTS##x4QI, > \ > - riscv_v_adjust_nunits (VNx##NSUBPARTS##x4QI##mode, > \ > - 4 * NSUBPARTS)); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1QI, 1); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1HI, 2); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1HF, 2); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1SI, 4); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1SF, 4); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x2QI, 1); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x2HI, 2); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x2HF, 2); > \ > - ADJUST_ALIGNMENT (VNx##NSUBPARTS##x4QI, 1); > - > -RVV_TUPLE_PARTIAL_MODES (2) > -RVV_TUPLE_PARTIAL_MODES (3) > -RVV_TUPLE_PARTIAL_MODES (4) > -RVV_TUPLE_PARTIAL_MODES (5) > -RVV_TUPLE_PARTIAL_MODES (6) > -RVV_TUPLE_PARTIAL_MODES (7) > -RVV_TUPLE_PARTIAL_MODES (8) > + ADJUST_ALIGNMENT (RVVM4x##NF##QI, 1); > \ > + ADJUST_ALIGNMENT (RVVM4x##NF##HI, 2); > \ > + ADJUST_ALIGNMENT (RVVM4x##NF##HF, 2); > \ > + ADJUST_ALIGNMENT (RVVM4x##NF##SI, 4); > \ > + ADJUST_ALIGNMENT (RVVM4x##NF##SF, 4); > \ > + ADJUST_ALIGNMENT (RVVM4x##NF##DI, 8); > \ > + ADJUST_ALIGNMENT (RVVM4x##NF##DF, 8); > + > +RVV_NF2_MODES (2) > > /* TODO: According to RISC-V 'V' ISA spec, the maximun vector length can > be 65536 for a single vector register which means the vector mode in > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index ff1e682f6d0..53088edf909 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -1550,37 +1550,20 @@ legitimize_move (rtx dest, rtx src) > /* VTYPE information for machine_mode. */ > struct mode_vtype_group > { > - enum vlmul_type vlmul_for_min_vlen32[NUM_MACHINE_MODES]; > - uint8_t ratio_for_min_vlen32[NUM_MACHINE_MODES]; > - enum vlmul_type vlmul_for_min_vlen64[NUM_MACHINE_MODES]; > - uint8_t ratio_for_min_vlen64[NUM_MACHINE_MODES]; > - enum vlmul_type vlmul_for_for_vlen128[NUM_MACHINE_MODES]; > - uint8_t ratio_for_for_vlen128[NUM_MACHINE_MODES]; > + enum vlmul_type vlmul[NUM_MACHINE_MODES]; > + uint8_t ratio[NUM_MACHINE_MODES]; > machine_mode subpart_mode[NUM_MACHINE_MODES]; > uint8_t nf[NUM_MACHINE_MODES]; > mode_vtype_group () > { > -#define ENTRY(MODE, REQUIREMENT, VLMUL_FOR_MIN_VLEN32, > RATIO_FOR_MIN_VLEN32, \ > - VLMUL_FOR_MIN_VLEN64, RATIO_FOR_MIN_VLEN64, > \ > - VLMUL_FOR_MIN_VLEN128, RATIO_FOR_MIN_VLEN128) > \ > - vlmul_for_min_vlen32[MODE##mode] =3D VLMUL_FOR_MIN_VLEN32; > \ > - ratio_for_min_vlen32[MODE##mode] =3D RATIO_FOR_MIN_VLEN32; > \ > - vlmul_for_min_vlen64[MODE##mode] =3D VLMUL_FOR_MIN_VLEN64; > \ > - ratio_for_min_vlen64[MODE##mode] =3D RATIO_FOR_MIN_VLEN64; > \ > - vlmul_for_for_vlen128[MODE##mode] =3D VLMUL_FOR_MIN_VLEN128; > \ > - ratio_for_for_vlen128[MODE##mode] =3D RATIO_FOR_MIN_VLEN128; > -#define TUPLE_ENTRY(MODE, REQUIREMENT, SUBPART_MODE, NF, > VLMUL_FOR_MIN_VLEN32, \ > - RATIO_FOR_MIN_VLEN32, VLMUL_FOR_MIN_VLEN64, > \ > - RATIO_FOR_MIN_VLEN64, VLMUL_FOR_MIN_VLEN128, > \ > - RATIO_FOR_MIN_VLEN128) > \ > +#define ENTRY(MODE, REQUIREMENT, VLMUL, RATIO) > \ > + vlmul[MODE##mode] =3D VLMUL; > \ > + ratio[MODE##mode] =3D RATIO; > +#define TUPLE_ENTRY(MODE, REQUIREMENT, SUBPART_MODE, NF, VLMUL, RATIO) > \ > subpart_mode[MODE##mode] =3D SUBPART_MODE##mode; > \ > nf[MODE##mode] =3D NF; > \ > - vlmul_for_min_vlen32[MODE##mode] =3D VLMUL_FOR_MIN_VLEN32; > \ > - ratio_for_min_vlen32[MODE##mode] =3D RATIO_FOR_MIN_VLEN32; > \ > - vlmul_for_min_vlen64[MODE##mode] =3D VLMUL_FOR_MIN_VLEN64; > \ > - ratio_for_min_vlen64[MODE##mode] =3D RATIO_FOR_MIN_VLEN64; > \ > - vlmul_for_for_vlen128[MODE##mode] =3D VLMUL_FOR_MIN_VLEN128; > \ > - ratio_for_for_vlen128[MODE##mode] =3D RATIO_FOR_MIN_VLEN128; > + vlmul[MODE##mode] =3D VLMUL; > \ > + ratio[MODE##mode] =3D RATIO; > #include "riscv-vector-switch.def" > #undef ENTRY > #undef TUPLE_ENTRY > @@ -1593,12 +1576,7 @@ static mode_vtype_group mode_vtype_infos; > enum vlmul_type > get_vlmul (machine_mode mode) > { > - if (TARGET_MIN_VLEN >=3D 128) > - return mode_vtype_infos.vlmul_for_for_vlen128[mode]; > - else if (TARGET_MIN_VLEN =3D=3D 32) > - return mode_vtype_infos.vlmul_for_min_vlen32[mode]; > - else > - return mode_vtype_infos.vlmul_for_min_vlen64[mode]; > + return mode_vtype_infos.vlmul[mode]; > } > > /* Return the NF value of the corresponding mode. */ > @@ -1610,8 +1588,8 @@ get_nf (machine_mode mode) > return mode_vtype_infos.nf[mode]; > } > > -/* Return the subpart mode of the tuple mode. For VNx2x1SImode, > - the subpart mode is VNx1SImode. This will help to build > +/* Return the subpart mode of the tuple mode. For RVVM2x2SImode, > + the subpart mode is RVVM2SImode. This will help to build > array/struct type in builtins. */ > machine_mode > get_subpart_mode (machine_mode mode) > @@ -1625,12 +1603,7 @@ get_subpart_mode (machine_mode mode) > unsigned int > get_ratio (machine_mode mode) > { > - if (TARGET_MIN_VLEN >=3D 128) > - return mode_vtype_infos.ratio_for_for_vlen128[mode]; > - else if (TARGET_MIN_VLEN =3D=3D 32) > - return mode_vtype_infos.ratio_for_min_vlen32[mode]; > - else > - return mode_vtype_infos.ratio_for_min_vlen64[mode]; > + return mode_vtype_infos.ratio[mode]; > } > > /* Get ta according to operand[tail_op_idx]. */ > @@ -2171,12 +2144,12 @@ preferred_simd_mode (scalar_mode mode) > /* We will disable auto-vectorization when TARGET_MIN_VLEN < 128 && > riscv_autovec_lmul < RVV_M2. Since GCC loop vectorizer report ICE > when we > enable -march=3Drv64gc_zve32* and -march=3Drv32gc_zve64*. in the > - 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have > - VNx1SImode in -march=3D*zve32* and VNx1DImode in -march=3D*zve64*, = they > are > - enabled in targetm. vector_mode_supported_p and SLP vectorizer will > try to > - use them. Currently, we can support auto-vectorization in > - -march=3Drv32_zve32x_zvl128b. Wheras, -march=3Drv32_zve32x_zvl32b or > - -march=3Drv32_zve32x_zvl64b are disabled. */ > + 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since both > + RVVM1SImode in -march=3D*zve32*_zvl32b and RVVM1DImode in > + -march=3D*zve64*_zvl64b are NUNITS =3D poly (1, 1), they will cause= ICE > in loop > + vectorizer when we enable them in this target hook. Currently, we c= an > + support auto-vectorization in -march=3Drv32_zve32x_zvl128b. Wheras, > + -march=3Drv32_zve32x_zvl32b or -march=3Drv32_zve32x_zvl64b are > disabled. */ > if (autovec_use_vlmax_p ()) > { > if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2) > @@ -2371,9 +2344,9 @@ autovectorize_vector_modes (vector_modes *modes, > bool) > poly_uint64 full_size > =3D BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul); > > - /* Start with a VNxYYQImode where YY is the number of units that > + /* Start with a RVVQImode where LMUL is the number of units > that > fit a whole vector. > - Then try YY =3D nunits / 2, nunits / 4 and nunits / 8 which > + Then try LMUL =3D nunits / 2, nunits / 4 and nunits / 8 which > is guided by the extensions we have available (vf2, vf4 and vf8). > > - full_size: Try using full vectors for all element types. > diff --git a/gcc/config/riscv/riscv-vector-builtins.cc > b/gcc/config/riscv/riscv-vector-builtins.cc > index 3a53b56effa..528dca7ae85 100644 > --- a/gcc/config/riscv/riscv-vector-builtins.cc > +++ b/gcc/config/riscv/riscv-vector-builtins.cc > @@ -109,10 +109,8 @@ const char *const operand_suffixes[NUM_OP_TYPES] =3D= { > > /* Static information about type suffix for each RVV type. */ > const rvv_builtin_suffixes type_suffixes[NUM_VECTOR_TYPES + 1] =3D { > -#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, > \ > - VECTOR_MODE_MIN_VLEN_128, VECTOR_MODE_MIN_VLEN_64, > \ > - VECTOR_MODE_MIN_VLEN_32, VECTOR_SUFFIX, > SCALAR_SUFFIX, \ > - VSETVL_SUFFIX) > \ > +#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE, > \ > + VECTOR_SUFFIX, SCALAR_SUFFIX, VSETVL_SUFFIX) > \ > {#VECTOR_SUFFIX, #SCALAR_SUFFIX, #VSETVL_SUFFIX}, > #define DEF_RVV_TUPLE_TYPE(NAME, NCHARS, ABI_NAME, SUBPART_TYPE, > SCALAR_TYPE, \ > NF, VECTOR_SUFFIX) > \ > @@ -2802,12 +2800,9 @@ register_builtin_types () > tree int64_type_node =3D get_typenode_from_name (INT64_TYPE); > > machine_mode mode; > -#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, > \ > - VECTOR_MODE_MIN_VLEN_128, VECTOR_MODE_MIN_VLEN_64, > \ > - VECTOR_MODE_MIN_VLEN_32, ARGS...) > \ > - mode =3D TARGET_MIN_VLEN >=3D 128 ? VECTOR_MODE_MIN_VLEN_128##= mode > \ > - : TARGET_MIN_VLEN >=3D 64 ? VECTOR_MODE_MIN_VLEN_64##mode > \ > - : VECTOR_MODE_MIN_VLEN_32##mode; > \ > +#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE, > \ > + ARGS...) > \ > + mode =3D VECTOR_MODE##mode; > \ > register_builtin_type (VECTOR_TYPE_##NAME, SCALAR_TYPE##_type_node, > mode); > #define DEF_RVV_TUPLE_TYPE(NAME, NCHARS, ABI_NAME, SUBPART_TYPE, > SCALAR_TYPE, \ > NF, VECTOR_SUFFIX) > \ > diff --git a/gcc/config/riscv/riscv-vector-builtins.def > b/gcc/config/riscv/riscv-vector-builtins.def > index 1e9457953f8..0e49480703b 100644 > --- a/gcc/config/riscv/riscv-vector-builtins.def > +++ b/gcc/config/riscv/riscv-vector-builtins.def > @@ -28,24 +28,19 @@ along with GCC; see the file COPYING3. If not see > "build_vector_type_for_mode". For "vint32m1_t", we use > "intSI_type_node" in > RV64. Otherwise, we use "long_integer_type_node". > 5.The 'VECTOR_MODE' is the machine modes of corresponding RVV type us= ed > - in "build_vector_type_for_mode" when TARGET_MIN_VLEN > 32. > - For example: VECTOR_MODE =3D VNx2SI for "vint32m1_t". > - 6.The 'VECTOR_MODE_MIN_VLEN_32' is the machine modes of corresponding > RVV > - type used in "build_vector_type_for_mode" when TARGET_MIN_VLEN =3D = 32. > For > - example: VECTOR_MODE_MIN_VLEN_32 =3D VNx1SI for "vint32m1_t". > - 7.The 'VECTOR_SUFFIX' define mode suffix for vector type. > + in "build_vector_type_for_mode". > + For example: VECTOR_MODE =3D RVVM1SImode for "vint32m1_t". > + 6.The 'VECTOR_SUFFIX' define mode suffix for vector type. > For example: type_suffixes[VECTOR_TYPE_vin32m1_t].vector =3D i32m1. > - 8.The 'SCALAR_SUFFIX' define mode suffix for scalar type. > + 7.The 'SCALAR_SUFFIX' define mode suffix for scalar type. > For example: type_suffixes[VECTOR_TYPE_vin32m1_t].scalar =3D i32. > - 9.The 'VSETVL_SUFFIX' define mode suffix for vsetvli instruction. > + 8.The 'VSETVL_SUFFIX' define mode suffix for vsetvli instruction. > For example: type_suffixes[VECTOR_TYPE_vin32m1_t].vsetvl =3D e32m1. > */ > > #ifndef DEF_RVV_TYPE > -#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, > \ > - VECTOR_MODE_MIN_VLEN_128, VECTOR_MODE_MIN_VLEN_64, > \ > - VECTOR_MODE_MIN_VLEN_32, VECTOR_SUFFIX, > SCALAR_SUFFIX, \ > - VSETVL_SUFFIX) > +#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE, > \ > + VECTOR_SUFFIX, SCALAR_SUFFIX, VSETVL_SUFFIX) > #endif > > #ifndef DEF_RVV_TUPLE_TYPE > @@ -101,47 +96,34 @@ along with GCC; see the file COPYING3. If not see > > /* SEW/LMUL =3D 64: > Only enable when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx1BImode when TARGET_MIN_VLEN < 128. > - Machine mode =3D VNx2BImode when TARGET_MIN_VLEN >=3D 128. */ > -DEF_RVV_TYPE (vbool64_t, 14, __rvv_bool64_t, boolean, VNx2BI, VNx1BI, > VOID, _b64, , ) > + Machine mode =3D RVVMF64BImode. */ > +DEF_RVV_TYPE (vbool64_t, 14, __rvv_bool64_t, boolean, RVVMF64BI, _b64, ,= ) > /* SEW/LMUL =3D 32: > - Machine mode =3D VNx2BImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx1BImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vbool32_t, 14, __rvv_bool32_t, boolean, VNx4BI, VNx2BI, > VNx1BI, _b32, , ) > + Machine mode =3D RVVMF32BImode. */ > +DEF_RVV_TYPE (vbool32_t, 14, __rvv_bool32_t, boolean, RVVMF32BI, _b32, ,= ) > /* SEW/LMUL =3D 16: > - Machine mode =3D VNx8BImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx2BImode when TARGET_MIN_VLEN =3D 32. > - Machine mode =3D VNx4BImode when TARGET_MIN_VLEN > 32. */ > -DEF_RVV_TYPE (vbool16_t, 14, __rvv_bool16_t, boolean, VNx8BI, VNx4BI, > VNx2BI, _b16, , ) > + Machine mode =3D RVVMF16BImode. */ > +DEF_RVV_TYPE (vbool16_t, 14, __rvv_bool16_t, boolean, RVVMF16BI, _b16, ,= ) > /* SEW/LMUL =3D 8: > - Machine mode =3D VNx16BImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx8BImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx4BImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vbool8_t, 13, __rvv_bool8_t, boolean, VNx16BI, VNx8BI, > VNx4BI, _b8, , ) > + Machine mode =3D RVVMF8BImode. */ > +DEF_RVV_TYPE (vbool8_t, 13, __rvv_bool8_t, boolean, RVVMF8BI, _b8, , ) > /* SEW/LMUL =3D 4: > - Machine mode =3D VNx32BImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx16BImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx8BImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vbool4_t, 13, __rvv_bool4_t, boolean, VNx32BI, VNx16BI, > VNx8BI, _b4, , ) > + Machine mode =3D RVVMF4BImode. */ > +DEF_RVV_TYPE (vbool4_t, 13, __rvv_bool4_t, boolean, RVVMF4BI, _b4, , ) > /* SEW/LMUL =3D 2: > - Machine mode =3D VNx64BImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx32BImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx16BImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vbool2_t, 13, __rvv_bool2_t, boolean, VNx64BI, VNx32BI, > VNx16BI, _b2, , ) > + Machine mode =3D RVVMF2BImode. */ > +DEF_RVV_TYPE (vbool2_t, 13, __rvv_bool2_t, boolean, RVVMF2BI, _b2, , ) > /* SEW/LMUL =3D 1: > - Machine mode =3D VNx128BImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx64BImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx32BImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vbool1_t, 13, __rvv_bool1_t, boolean, VNx128BI, VNx64BI, > VNx32BI, _b1, , ) > + Machine mode =3D RVVM1BImode. */ > +DEF_RVV_TYPE (vbool1_t, 13, __rvv_bool1_t, boolean, RVVM1BI, _b1, , ) > > /* LMUL =3D 1/8: > Only enble when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx1QImode when TARGET_MIN_VLEN < 128. > - Machine mode =3D VNx2QImode when TARGET_MIN_VLEN >=3D 128. */ > -DEF_RVV_TYPE (vint8mf8_t, 15, __rvv_int8mf8_t, int8, VNx2QI, VNx1QI, > VOID, _i8mf8, _i8, > + Machine mode =3D RVVMF8QImode. */ > +DEF_RVV_TYPE (vint8mf8_t, 15, __rvv_int8mf8_t, int8, RVVMF8QI, _i8mf8, > _i8, > + _e8mf8) > +DEF_RVV_TYPE (vuint8mf8_t, 16, __rvv_uint8mf8_t, uint8, RVVMF8QI, _u8mf8, > _u8, > _e8mf8) > -DEF_RVV_TYPE (vuint8mf8_t, 16, __rvv_uint8mf8_t, uint8, VNx2QI, VNx1QI, > VOID, _u8mf8, > - _u8, _e8mf8) > /* Define tuple types for SEW =3D 8, LMUL =3D MF8. */ > DEF_RVV_TUPLE_TYPE (vint8mf8x2_t, 17, __rvv_int8mf8x2_t, vint8mf8_t, > int8, 2, _i8mf8x2) > DEF_RVV_TUPLE_TYPE (vuint8mf8x2_t, 18, __rvv_uint8mf8x2_t, vuint8mf8_t, > uint8, 2, _u8mf8x2) > @@ -158,13 +140,11 @@ DEF_RVV_TUPLE_TYPE (vuint8mf8x7_t, 18, > __rvv_uint8mf8x7_t, vuint8mf8_t, uint8, 7 > DEF_RVV_TUPLE_TYPE (vint8mf8x8_t, 17, __rvv_int8mf8x8_t, vint8mf8_t, > int8, 8, _i8mf8x8) > DEF_RVV_TUPLE_TYPE (vuint8mf8x8_t, 18, __rvv_uint8mf8x8_t, vuint8mf8_t, > uint8, 8, _u8mf8x8) > /* LMUL =3D 1/4: > - Machine mode =3D VNx4QImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx2QImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx1QImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vint8mf4_t, 15, __rvv_int8mf4_t, int8, VNx4QI, VNx2QI, > VNx1QI, _i8mf4, > - _i8, _e8mf4) > -DEF_RVV_TYPE (vuint8mf4_t, 16, __rvv_uint8mf4_t, uint8, VNx4QI, VNx2QI, > VNx1QI, _u8mf4, > - _u8, _e8mf4) > + Machine mode =3D RVVMF4QImode. */ > +DEF_RVV_TYPE (vint8mf4_t, 15, __rvv_int8mf4_t, int8, RVVMF4QI, _i8mf4, > _i8, > + _e8mf4) > +DEF_RVV_TYPE (vuint8mf4_t, 16, __rvv_uint8mf4_t, uint8, RVVMF4QI, _u8mf4, > _u8, > + _e8mf4) > /* Define tuple types for SEW =3D 8, LMUL =3D MF4. */ > DEF_RVV_TUPLE_TYPE (vint8mf4x2_t, 17, __rvv_int8mf4x2_t, vint8mf4_t, > int8, 2, _i8mf4x2) > DEF_RVV_TUPLE_TYPE (vuint8mf4x2_t, 18, __rvv_uint8mf4x2_t, vuint8mf4_t, > uint8, 2, _u8mf4x2) > @@ -181,13 +161,11 @@ DEF_RVV_TUPLE_TYPE (vuint8mf4x7_t, 18, > __rvv_uint8mf4x7_t, vuint8mf4_t, uint8, 7 > DEF_RVV_TUPLE_TYPE (vint8mf4x8_t, 17, __rvv_int8mf4x8_t, vint8mf4_t, > int8, 8, _i8mf4x8) > DEF_RVV_TUPLE_TYPE (vuint8mf4x8_t, 18, __rvv_uint8mf4x8_t, vuint8mf4_t, > uint8, 8, _u8mf4x8) > /* LMUL =3D 1/2: > - Machine mode =3D VNx8QImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx4QImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx2QImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vint8mf2_t, 15, __rvv_int8mf2_t, int8, VNx8QI, VNx4QI, > VNx2QI, _i8mf2, > - _i8, _e8mf2) > -DEF_RVV_TYPE (vuint8mf2_t, 16, __rvv_uint8mf2_t, uint8, VNx8QI, VNx4QI, > VNx2QI, _u8mf2, > - _u8, _e8mf2) > + Machine mode =3D RVVMF2QImode. */ > +DEF_RVV_TYPE (vint8mf2_t, 15, __rvv_int8mf2_t, int8, RVVMF2QI, _i8mf2, > _i8, > + _e8mf2) > +DEF_RVV_TYPE (vuint8mf2_t, 16, __rvv_uint8mf2_t, uint8, RVVMF2QI, _u8mf2, > _u8, > + _e8mf2) > /* Define tuple types for SEW =3D 8, LMUL =3D MF2. */ > DEF_RVV_TUPLE_TYPE (vint8mf2x2_t, 17, __rvv_int8mf2x2_t, vint8mf2_t, > int8, 2, _i8mf2x2) > DEF_RVV_TUPLE_TYPE (vuint8mf2x2_t, 18, __rvv_uint8mf2x2_t, vuint8mf2_t, > uint8, 2, _u8mf2x2) > @@ -204,13 +182,10 @@ DEF_RVV_TUPLE_TYPE (vuint8mf2x7_t, 18, > __rvv_uint8mf2x7_t, vuint8mf2_t, uint8, 7 > DEF_RVV_TUPLE_TYPE (vint8mf2x8_t, 17, __rvv_int8mf2x8_t, vint8mf2_t, > int8, 8, _i8mf2x8) > DEF_RVV_TUPLE_TYPE (vuint8mf2x8_t, 18, __rvv_uint8mf2x8_t, vuint8mf2_t, > uint8, 8, _u8mf2x8) > /* LMUL =3D 1: > - Machine mode =3D VNx16QImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx8QImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx4QImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vint8m1_t, 14, __rvv_int8m1_t, int8, VNx16QI, VNx8QI, > VNx4QI, _i8m1, _i8, > + Machine mode =3D RVVM1QImode. */ > +DEF_RVV_TYPE (vint8m1_t, 14, __rvv_int8m1_t, int8, RVVM1QI, _i8m1, _i8, > _e8m1) > +DEF_RVV_TYPE (vuint8m1_t, 15, __rvv_uint8m1_t, uint8, RVVM1QI, _u8m1, _u= 8, > _e8m1) > -DEF_RVV_TYPE (vuint8m1_t, 15, __rvv_uint8m1_t, uint8, VNx16QI, VNx8QI, > VNx4QI, _u8m1, > - _u8, _e8m1) > /* Define tuple types for SEW =3D 8, LMUL =3D M1. */ > DEF_RVV_TUPLE_TYPE (vint8m1x2_t, 16, __rvv_int8m1x2_t, vint8m1_t, int8, > 2, _i8m1x2) > DEF_RVV_TUPLE_TYPE (vuint8m1x2_t, 17, __rvv_uint8m1x2_t, vuint8m1_t, > uint8, 2, _u8m1x2) > @@ -227,13 +202,10 @@ DEF_RVV_TUPLE_TYPE (vuint8m1x7_t, 17, > __rvv_uint8m1x7_t, vuint8m1_t, uint8, 7, _ > DEF_RVV_TUPLE_TYPE (vint8m1x8_t, 16, __rvv_int8m1x8_t, vint8m1_t, int8, > 8, _i8m1x8) > DEF_RVV_TUPLE_TYPE (vuint8m1x8_t, 17, __rvv_uint8m1x8_t, vuint8m1_t, > uint8, 8, _u8m1x8) > /* LMUL =3D 2: > - Machine mode =3D VNx32QImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx16QImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx8QImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vint8m2_t, 14, __rvv_int8m2_t, int8, VNx32QI, VNx16QI, > VNx8QI, _i8m2, _i8, > + Machine mode =3D RVVM2QImode. */ > +DEF_RVV_TYPE (vint8m2_t, 14, __rvv_int8m2_t, int8, RVVM2QI, _i8m2, _i8, > _e8m2) > +DEF_RVV_TYPE (vuint8m2_t, 15, __rvv_uint8m2_t, uint8, RVVM2QI, _u8m2, _u= 8, > _e8m2) > -DEF_RVV_TYPE (vuint8m2_t, 15, __rvv_uint8m2_t, uint8, VNx32QI, VNx16QI, > VNx8QI, _u8m2, > - _u8, _e8m2) > /* Define tuple types for SEW =3D 8, LMUL =3D M2. */ > DEF_RVV_TUPLE_TYPE (vint8m2x2_t, 16, __rvv_int8m2x2_t, vint8m2_t, int8, > 2, _i8m2x2) > DEF_RVV_TUPLE_TYPE (vuint8m2x2_t, 17, __rvv_uint8m2x2_t, vuint8m2_t, > uint8, 2, _u8m2x2) > @@ -242,33 +214,26 @@ DEF_RVV_TUPLE_TYPE (vuint8m2x3_t, 17, > __rvv_uint8m2x3_t, vuint8m2_t, uint8, 3, _ > DEF_RVV_TUPLE_TYPE (vint8m2x4_t, 16, __rvv_int8m2x4_t, vint8m2_t, int8, > 4, _i8m2x4) > DEF_RVV_TUPLE_TYPE (vuint8m2x4_t, 17, __rvv_uint8m2x4_t, vuint8m2_t, > uint8, 4, _u8m2x4) > /* LMUL =3D 4: > - Machine mode =3D VNx64QImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx32QImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx16QImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vint8m4_t, 14, __rvv_int8m4_t, int8, VNx64QI, VNx32QI, > VNx16QI, _i8m4, _i8, > + Machine mode =3D RVVM4QImode. */ > +DEF_RVV_TYPE (vint8m4_t, 14, __rvv_int8m4_t, int8, RVVM4QI, _i8m4, _i8, > _e8m4) > +DEF_RVV_TYPE (vuint8m4_t, 15, __rvv_uint8m4_t, uint8, RVVM4QI, _u8m4, _u= 8, > _e8m4) > -DEF_RVV_TYPE (vuint8m4_t, 15, __rvv_uint8m4_t, uint8, VNx64QI, VNx32QI, > VNx16QI, _u8m4, > - _u8, _e8m4) > /* Define tuple types for SEW =3D 8, LMUL =3D M4. */ > DEF_RVV_TUPLE_TYPE (vint8m4x2_t, 16, __rvv_int8m4x2_t, vint8m4_t, int8, > 2, _i8m4x2) > DEF_RVV_TUPLE_TYPE (vuint8m4x2_t, 17, __rvv_uint8m4x2_t, vuint8m4_t, > uint8, 2, _u8m4x2) > /* LMUL =3D 8: > - Machine mode =3D VNx128QImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx64QImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx32QImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vint8m8_t, 14, __rvv_int8m8_t, int8, VNx128QI, VNx64QI, > VNx32QI, _i8m8, _i8, > + Machine mode =3D RVVM8QImode. */ > +DEF_RVV_TYPE (vint8m8_t, 14, __rvv_int8m8_t, int8, RVVM8QI, _i8m8, _i8, > _e8m8) > +DEF_RVV_TYPE (vuint8m8_t, 15, __rvv_uint8m8_t, uint8, RVVM8QI, _u8m8, _u= 8, > _e8m8) > -DEF_RVV_TYPE (vuint8m8_t, 15, __rvv_uint8m8_t, uint8, VNx128QI, VNx64QI, > VNx32QI, _u8m8, > - _u8, _e8m8) > > /* LMUL =3D 1/4: > Only enble when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx1HImode when TARGET_MIN_VLEN < 128. > - Machine mode =3D VNx2HImode when TARGET_MIN_VLEN >=3D 128. */ > -DEF_RVV_TYPE (vint16mf4_t, 16, __rvv_int16mf4_t, int16, VNx2HI, VNx1HI, > VOID, _i16mf4, > - _i16, _e16mf4) > -DEF_RVV_TYPE (vuint16mf4_t, 17, __rvv_uint16mf4_t, uint16, VNx2HI, > VNx1HI, VOID, > - _u16mf4, _u16, _e16mf4) > + Machine mode =3D RVVMF4HImode. */ > +DEF_RVV_TYPE (vint16mf4_t, 16, __rvv_int16mf4_t, int16, RVVMF4HI, > _i16mf4, _i16, > + _e16mf4) > +DEF_RVV_TYPE (vuint16mf4_t, 17, __rvv_uint16mf4_t, uint16, RVVMF4HI, > _u16mf4, > + _u16, _e16mf4) > /* Define tuple types for SEW =3D 16, LMUL =3D MF4. */ > DEF_RVV_TUPLE_TYPE (vint16mf4x2_t, 18, __rvv_int16mf4x2_t, vint16mf4_t, > int16, 2, _i16mf4x2) > DEF_RVV_TUPLE_TYPE (vuint16mf4x2_t, 19, __rvv_uint16mf4x2_t, > vuint16mf4_t, uint16, 2, _u16mf4x2) > @@ -285,13 +250,11 @@ DEF_RVV_TUPLE_TYPE (vuint16mf4x7_t, 19, > __rvv_uint16mf4x7_t, vuint16mf4_t, uint1 > DEF_RVV_TUPLE_TYPE (vint16mf4x8_t, 18, __rvv_int16mf4x8_t, vint16mf4_t, > int16, 8, _i16mf4x8) > DEF_RVV_TUPLE_TYPE (vuint16mf4x8_t, 19, __rvv_uint16mf4x8_t, > vuint16mf4_t, uint16, 8, _u16mf4x8) > /* LMUL =3D 1/2: > - Machine mode =3D VNx4HImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx2HImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx1HImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vint16mf2_t, 16, __rvv_int16mf2_t, int16, VNx4HI, VNx2HI, > VNx1HI, _i16mf2, > - _i16, _e16mf2) > -DEF_RVV_TYPE (vuint16mf2_t, 17, __rvv_uint16mf2_t, uint16, VNx4HI, > VNx2HI, VNx1HI, > - _u16mf2, _u16, _e16mf2) > + Machine mode =3D RVVMF2HImode. */ > +DEF_RVV_TYPE (vint16mf2_t, 16, __rvv_int16mf2_t, int16, RVVMF2HI, > _i16mf2, _i16, > + _e16mf2) > +DEF_RVV_TYPE (vuint16mf2_t, 17, __rvv_uint16mf2_t, uint16, RVVMF2HI, > _u16mf2, > + _u16, _e16mf2) > /* Define tuple types for SEW =3D 16, LMUL =3D MF2. */ > DEF_RVV_TUPLE_TYPE (vint16mf2x2_t, 18, __rvv_int16mf2x2_t, vint16mf2_t, > int16, 2, _i16mf2x2) > DEF_RVV_TUPLE_TYPE (vuint16mf2x2_t, 19, __rvv_uint16mf2x2_t, > vuint16mf2_t, uint16, 2, _u16mf2x2) > @@ -308,13 +271,11 @@ DEF_RVV_TUPLE_TYPE (vuint16mf2x7_t, 19, > __rvv_uint16mf2x7_t, vuint16mf2_t, uint1 > DEF_RVV_TUPLE_TYPE (vint16mf2x8_t, 18, __rvv_int16mf2x8_t, vint16mf2_t, > int16, 8, _i16mf2x8) > DEF_RVV_TUPLE_TYPE (vuint16mf2x8_t, 19, __rvv_uint16mf2x8_t, > vuint16mf2_t, uint16, 8, _u16mf2x8) > /* LMUL =3D 1: > - Machine mode =3D VNx8HImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx4HImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx2HImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vint16m1_t, 15, __rvv_int16m1_t, int16, VNx8HI, VNx4HI, > VNx2HI, _i16m1, > - _i16, _e16m1) > -DEF_RVV_TYPE (vuint16m1_t, 16, __rvv_uint16m1_t, uint16, VNx8HI, VNx4HI, > VNx2HI, _u16m1, > - _u16, _e16m1) > + Machine mode =3D RVVM1HImode. */ > +DEF_RVV_TYPE (vint16m1_t, 15, __rvv_int16m1_t, int16, RVVM1HI, _i16m1, > _i16, > + _e16m1) > +DEF_RVV_TYPE (vuint16m1_t, 16, __rvv_uint16m1_t, uint16, RVVM1HI, _u16m1, > _u16, > + _e16m1) > /* Define tuple types for SEW =3D 16, LMUL =3D M1. */ > DEF_RVV_TUPLE_TYPE (vint16m1x2_t, 17, __rvv_int16m1x2_t, vint16m1_t, > int16, 2, _i16m1x2) > DEF_RVV_TUPLE_TYPE (vuint16m1x2_t, 18, __rvv_uint16m1x2_t, vuint16m1_t, > uint16, 2, _u16m1x2) > @@ -331,13 +292,11 @@ DEF_RVV_TUPLE_TYPE (vuint16m1x7_t, 18, > __rvv_uint16m1x7_t, vuint16m1_t, uint16, > DEF_RVV_TUPLE_TYPE (vint16m1x8_t, 17, __rvv_int16m1x8_t, vint16m1_t, > int16, 8, _i16m1x8) > DEF_RVV_TUPLE_TYPE (vuint16m1x8_t, 18, __rvv_uint16m1x8_t, vuint16m1_t, > uint16, 8, _u16m1x8) > /* LMUL =3D 2: > - Machine mode =3D VNx16HImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx8HImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx4HImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vint16m2_t, 15, __rvv_int16m2_t, int16, VNx16HI, VNx8HI, > VNx4HI, _i16m2, > - _i16, _e16m2) > -DEF_RVV_TYPE (vuint16m2_t, 16, __rvv_uint16m2_t, uint16, VNx16HI, VNx8HI, > VNx4HI, _u16m2, > - _u16, _e16m2) > + Machine mode =3D RVVM1H2mode. */ > +DEF_RVV_TYPE (vint16m2_t, 15, __rvv_int16m2_t, int16, RVVM2HI, _i16m2, > _i16, > + _e16m2) > +DEF_RVV_TYPE (vuint16m2_t, 16, __rvv_uint16m2_t, uint16, RVVM2HI, _u16m2, > _u16, > + _e16m2) > /* Define tuple types for SEW =3D 16, LMUL =3D M2. */ > DEF_RVV_TUPLE_TYPE (vint16m2x2_t, 17, __rvv_int16m2x2_t, vint16m2_t, > int16, 2, _i16m2x2) > DEF_RVV_TUPLE_TYPE (vuint16m2x2_t, 18, __rvv_uint16m2x2_t, vuint16m2_t, > uint16, 2, _u16m2x2) > @@ -346,33 +305,28 @@ DEF_RVV_TUPLE_TYPE (vuint16m2x3_t, 18, > __rvv_uint16m2x3_t, vuint16m2_t, uint16, > DEF_RVV_TUPLE_TYPE (vint16m2x4_t, 17, __rvv_int16m2x4_t, vint16m2_t, > int16, 4, _i16m2x4) > DEF_RVV_TUPLE_TYPE (vuint16m2x4_t, 18, __rvv_uint16m2x4_t, vuint16m2_t, > uint16, 4, _u16m2x4) > /* LMUL =3D 4: > - Machine mode =3D VNx32HImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx16HImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx8HImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vint16m4_t, 15, __rvv_int16m4_t, int16, VNx32HI, VNx16HI, > VNx8HI, _i16m4, > - _i16, _e16m4) > -DEF_RVV_TYPE (vuint16m4_t, 16, __rvv_uint16m4_t, uint16, VNx32HI, > VNx16HI, VNx8HI, > - _u16m4, _u16, _e16m4) > + Machine mode =3D RVVM4HImode. */ > +DEF_RVV_TYPE (vint16m4_t, 15, __rvv_int16m4_t, int16, RVVM4HI, _i16m4, > _i16, > + _e16m4) > +DEF_RVV_TYPE (vuint16m4_t, 16, __rvv_uint16m4_t, uint16, RVVM4HI, _u16m4, > _u16, > + _e16m4) > /* Define tuple types for SEW =3D 16, LMUL =3D M4. */ > DEF_RVV_TUPLE_TYPE (vint16m4x2_t, 17, __rvv_int16m4x2_t, vint16m4_t, > int16, 2, _i16m4x2) > DEF_RVV_TUPLE_TYPE (vuint16m4x2_t, 18, __rvv_uint16m4x2_t, vuint16m4_t, > uint16, 2, _u16m4x2) > /* LMUL =3D 8: > - Machine mode =3D VNx64HImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx32HImode when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx16HImode when TARGET_MIN_VLEN =3D 32. */ > -DEF_RVV_TYPE (vint16m8_t, 15, __rvv_int16m8_t, int16, VNx64HI, VNx32HI, > VNx16HI, _i16m8, > - _i16, _e16m8) > -DEF_RVV_TYPE (vuint16m8_t, 16, __rvv_uint16m8_t, uint16, VNx64HI, > VNx32HI, VNx16HI, > - _u16m8, _u16, _e16m8) > + Machine mode =3D RVVM8HImode. */ > +DEF_RVV_TYPE (vint16m8_t, 15, __rvv_int16m8_t, int16, RVVM8HI, _i16m8, > _i16, > + _e16m8) > +DEF_RVV_TYPE (vuint16m8_t, 16, __rvv_uint16m8_t, uint16, RVVM8HI, _u16m8, > _u16, > + _e16m8) > > /* LMUL =3D 1/2: > Only enble when TARGET_MIN_VLEN > 32. > - Machine mode =3D VNx1SImode when TARGET_MIN_VLEN < 128. > - Machine mode =3D VNx2SImode when TARGET_MIN_VLEN >=3D 128. */ > -DEF_RVV_TYPE (vint32mf2_t, 16, __rvv_int32mf2_t, int32, VNx2SI, VNx1SI, > VOID, _i32mf2, > - _i32, _e32mf2) > -DEF_RVV_TYPE (vuint32mf2_t, 17, __rvv_uint32mf2_t, uint32, VNx2SI, > VNx1SI, VOID, > - _u32mf2, _u32, _e32mf2) > + Machine mode =3D RVVMF2SImode. */ > +DEF_RVV_TYPE (vint32mf2_t, 16, __rvv_int32mf2_t, int32, RVVMF2SI, > _i32mf2, _i32, > + _e32mf2) > +DEF_RVV_TYPE (vuint32mf2_t, 17, __rvv_uint32mf2_t, uint32, RVVMF2SI, > _u32mf2, > + _u32, _e32mf2) > /* Define tuple types for SEW =3D 32, LMUL =3D MF2. */ > DEF_RVV_TUPLE_TYPE (vint32mf2x2_t, 18, __rvv_int32mf2x2_t, vint32mf2_t, > int32, 2, _i32mf2x2) > DEF_RVV_TUPLE_TYPE (vuint32mf2x2_t, 19, __rvv_uint32mf2x2_t, > vuint32mf2_t, uint32, 2, _u32mf2x2) > @@ -389,13 +343,11 @@ DEF_RVV_TUPLE_TYPE (vuint32mf2x7_t, 19, > __rvv_uint32mf2x7_t, vuint32mf2_t, uint3 > DEF_RVV_TUPLE_TYPE (vint32mf2x8_t, 18, __rvv_int32mf2x8_t, vint32mf2_t, > int32, 8, _i32mf2x8) > DEF_RVV_TUPLE_TYPE (vuint32mf2x8_t, 19, __rvv_uint32mf2x8_t, > vuint32mf2_t, uint32, 8, _u32mf2x8) > /* LMUL =3D 1: > - Machine mode =3D VNx4SImode when TARGET_MIN_VLEN >=3D 128. > - Machine mode =3D VNx2SImode when TARGET_MIN_VLEN > 32. > --000000000000854c750600e1bc32--