> On Thu 8. Jun 2023 at 09:35, Kito Cheng via Gcc-patches <
> gcc-patches@gcc.gnu.org> wrote:
>
> > > diff --git a/gcc/config/riscv/riscv-cores.def
> > b/gcc/config/riscv/riscv-cores.def
> > > index 7d87ab7ce28..4078439e562 100644
> > > --- a/gcc/config/riscv/riscv-cores.def
> > > +++ b/gcc/config/riscv/riscv-cores.def
> > > @@ -38,6 +38,7 @@ RISCV_TUNE("sifive-3-series", generic,
> > rocket_tune_info)
> > >  RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
> > >  RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
> > >  RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
> > > +RISCV_TUNE("veyron-v1", veyron_v1, veyron_v1_tune_info)
> > >  RISCV_TUNE("size", generic, optimize_size_tune_info)
> > >
> > >  #undef RISCV_TUNE
> > > @@ -77,4 +78,7 @@ RISCV_CORE("thead-c906",
> > "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
> > >                               "xtheadcondmov_xtheadfmemidx_xtheadmac_"
> > >                               "xtheadmemidx_xtheadmempair_xtheadsync",
> > >                               "thead-c906")
> > > +
> > > +RISCV_CORE("veyron-v1",
> >  "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops",
> > > +                             "veyron-v1")
> >
> > Seems like xventanacondops have not in the trunk yet, I saw Jeff has
> > approved before but not commit yet
>
>
> We couldn’t apply back then, as Veyro -V1 had been unnannounced.
> Can we move this forward now?
>

Oh, okay I got the awkness point...I am ok with that on gcc land, but I
would like binutils support that first, or remove the extension from the
mcpu for temporary before binutils support, otherwise it just a broken
support for that CPU on trunk gcc.




> Philipp.
>
> >
>