From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe33.google.com (mail-vs1-xe33.google.com [IPv6:2607:f8b0:4864:20::e33]) by sourceware.org (Postfix) with ESMTPS id 6A563385703F for ; Thu, 8 Jun 2023 10:22:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6A563385703F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe33.google.com with SMTP id ada2fe7eead31-437e8282c1fso56834137.2 for ; Thu, 08 Jun 2023 03:22:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686219749; x=1688811749; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=+zI684pupgpYi9n1SSD/rURxiuOGxSU27zfuamA4OO8=; b=ZST5u9+c5yuybkXD+C6IjpVqeg2mqYxeaXVeR35fUjeBzQQyXUk3o9iOE/Q2f2jyCg DwXJwrD0s1a6NHss1ndMC0YoxEPEqHC1KmhVJ31dEBr5UGw07n+AHtay01qsR0YX0Rnb /mC5Ul5pXOxoKqgwOdWeUgq+BGTHyBAqmC4r720wvI3H+uWb3So5nc0fN80kpEBnl1OT cMXMNzH1uW3nArBYS+lQ/2+YLzVmEasE/3MPoOlneTysLFi2kiu4L7cVP/cBrMnPBOY8 EoYzjzbO8QwQGUZ4iedj0qCay6RvSaF2V++XvypW0aFMN16EFYQJ8OZD0xJhbHUsxzWo GZzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686219749; x=1688811749; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=+zI684pupgpYi9n1SSD/rURxiuOGxSU27zfuamA4OO8=; b=XPKlij0CuEZpJJb1kh+ZPXMP9yWuuAWSHx3Tw4RCvNh+YLftXA9ZwlhjihgskTt6Rw eEBoKvRzLW4FFa0Tkq+8WAeOTpeSmxONGE9inc1sIsBUT2d8JeyrwH3nhzN4BwMFukCZ fnQUMJvCOtqZySOhIW/I7Iw48Rbi1eCYU3tln4Wma65CziNZnMB99ytXgswgkTPkNDtx BKUOkVmFgN4sz3d4OHfVzUYbTiR/wGGZQ8L5TI4wnZWe1+V7wfG8kHZHBnSnACgqrD0Z 1o0//aAq6+UYqWVIs4PKVtqsmv74CL0r4i6J8uV36xsRZ2XD+57SHhuCw8ijHo9JAuUH OsDw== X-Gm-Message-State: AC+VfDxr1RLsgauTV+HPxlKE6fWUU56WtE/H1t13srUI10Sx0U+0y21L 6rEFUwU9VQbvSfXSSyOKTq6E8z2ExGoxwe39TKU= X-Google-Smtp-Source: ACHHUZ5wBISaF57G3fKJfCHbo9JwfFG5nOAVesYCyCncyL+oVdBEE0AMYXzcMZZAqu1Bdq6ZTGJubGVqElRrmmPZRuc= X-Received: by 2002:a05:6102:134b:b0:42f:e944:7ea0 with SMTP id j11-20020a056102134b00b0042fe9447ea0mr1267299vsl.6.1686219749585; Thu, 08 Jun 2023 03:22:29 -0700 (PDT) MIME-Version: 1.0 References: <20230607131749.82794-1-rzinsly@ventanamicro.com> In-Reply-To: From: Kito Cheng Date: Thu, 8 Jun 2023 18:22:17 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add Veyron V1 pipeline description To: Philipp Tomsich Cc: Raphael Moreira Zinsly , GCC Patches , Jeff Law Content-Type: multipart/alternative; boundary="0000000000002ff83205fd9ba177" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000002ff83205fd9ba177 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable > On Thu 8. Jun 2023 at 09:35, Kito Cheng via Gcc-patches < > gcc-patches@gcc.gnu.org> wrote: > > > > diff --git a/gcc/config/riscv/riscv-cores.def > > b/gcc/config/riscv/riscv-cores.def > > > index 7d87ab7ce28..4078439e562 100644 > > > --- a/gcc/config/riscv/riscv-cores.def > > > +++ b/gcc/config/riscv/riscv-cores.def > > > @@ -38,6 +38,7 @@ RISCV_TUNE("sifive-3-series", generic, > > rocket_tune_info) > > > RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) > > > RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) > > > RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) > > > +RISCV_TUNE("veyron-v1", veyron_v1, veyron_v1_tune_info) > > > RISCV_TUNE("size", generic, optimize_size_tune_info) > > > > > > #undef RISCV_TUNE > > > @@ -77,4 +78,7 @@ RISCV_CORE("thead-c906", > > "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" > > > "xtheadcondmov_xtheadfmemidx_xtheadmac_" > > > "xtheadmemidx_xtheadmempair_xtheadsync", > > > "thead-c906") > > > + > > > +RISCV_CORE("veyron-v1", > > "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops", > > > + "veyron-v1") > > > > Seems like xventanacondops have not in the trunk yet, I saw Jeff has > > approved before but not commit yet > > > We couldn=E2=80=99t apply back then, as Veyro -V1 had been unnannounced. > Can we move this forward now? > Oh, okay I got the awkness point...I am ok with that on gcc land, but I would like binutils support that first, or remove the extension from the mcpu for temporary before binutils support, otherwise it just a broken support for that CPU on trunk gcc. > Philipp. > > > > --0000000000002ff83205fd9ba177--