From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by sourceware.org (Postfix) with ESMTPS id 39BD13888C4F for ; Fri, 18 Mar 2022 06:52:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 39BD13888C4F Received: by mail-ed1-x52f.google.com with SMTP id w4so9142337edc.7 for ; Thu, 17 Mar 2022 23:52:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=5bUI8N9ZcUOHO7LmDjX2bPqoXlhvYY5ONoSuOG85s00=; b=ft3fbXCRkeNDKPFILvlKSjPV7jzhovk1kszbLNcZWetyQ2H0AFIqXC4GCXCPvzVAOO mfngDDaBO3LRiZYsWojXwLRKEiqCh2uDezMQ+ebFXoUilXmKBBjeKL5yW3FQj8OGxIrp cdB7eM4teiNr6P+x+OOKGocl/C6NUdiMeXgIUVRd4970wEm4TD5HiXFxwJMB7ESAjwn6 wSWdCgv61goVKnUT4ZN2eTmXYKguKMdg16W9HVDusTvQrdBj//LqXuqulBAEzHm6PDdf vaOXHmZfTI3YJw8yOoi82nYAGREBl8kbtEyhmDFPEaYs+Qk+1Zy35VZzwJwFE0jE2YGi fC4Q== X-Gm-Message-State: AOAM530hR2H7VvRJfCzC74d9EEcsx+DoCBMkdPUb9hbIoCuZLugqFOP2 u/Z5tsJzGkVtrRJ/EPmuJAu/SKi8ZAISfkwgCs4= X-Google-Smtp-Source: ABdhPJzJSCMe7tSDc2ilSl98eHcvCqh3PbXO/aza0RMpnuLcanYu8Z6YEnAa8tGxQkdM6+t0cdRTXKWjqhmXZ52SJtQ= X-Received: by 2002:aa7:c1cd:0:b0:419:fdb:e17e with SMTP id d13-20020aa7c1cd000000b004190fdbe17emr851711edp.364.1647586335659; Thu, 17 Mar 2022 23:52:15 -0700 (PDT) MIME-Version: 1.0 References: <20220315091013.1036-1-shihua@iscas.ac.cn> In-Reply-To: <20220315091013.1036-1-shihua@iscas.ac.cn> From: Kito Cheng Date: Fri, 18 Mar 2022 14:52:04 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Implement ZTSO extension. To: =?UTF-8?B?5buW5LuV5Y2O?= Cc: GCC Patches , Christoph Muellner , Andrew Waterman , Kito Cheng Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Mar 2022 06:52:18 -0000 Hi Shi-Hua: Thanks, this patch is LGTM, but I would defer that until stage 1, because the binutils part isn't merget yet. On Tue, Mar 15, 2022 at 5:10 PM wrote: > > From: LiaoShihua > > ZTSO is the extension of tatol store order model. > This extension adds no new instructions to the ISA, and you can use it with arch "ztso". > If you use it, TSO flag will be generate in the ELF header. > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: define new arch. > * config/riscv/riscv-opts.h (MASK_ZTSO): Ditto. > (TARGET_ZTSO):Ditto. > * config/riscv/riscv.opt:Ditto. > > --- > gcc/common/config/riscv/riscv-common.cc | 4 +++- > gcc/config/riscv/riscv-opts.h | 3 +++ > gcc/config/riscv/riscv.opt | 3 +++ > 3 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc > index a904893b9ed..f4730b991d7 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -185,6 +185,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = > {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, > {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, > > + {"ztso", ISA_SPEC_CLASS_NONE, 0, 1}, > + > /* Terminate the list. */ > {NULL, ISA_SPEC_CLASS_NONE, 0, 0} > }; > @@ -1080,7 +1082,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = > {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, > {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, > > - > + {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO}, > {NULL, NULL, 0} > }; > > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h > index 929e4e3a7c5..9cb5f2a550a 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -136,4 +136,7 @@ enum stack_protector_guard { > #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) > #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) > > +#define MASK_ZTSO (1 << 0) > +#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0) > + > #endif /* ! GCC_RISCV_OPTS_H */ > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index 9fffc08220d..6128bfa31dc 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -209,6 +209,9 @@ int riscv_vector_eew_flags > TargetVariable > int riscv_zvl_flags > > +TargetVariable > +int riscv_ztso_subext > + > Enum > Name(isa_spec_class) Type(enum riscv_isa_spec_class) > Supported ISA specs (for use with the -misa-spec= option): > -- > 2.31.1.windows.1 >