From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe2f.google.com (mail-vs1-xe2f.google.com [IPv6:2607:f8b0:4864:20::e2f]) by sourceware.org (Postfix) with ESMTPS id E92903858D33 for ; Mon, 13 Feb 2023 03:03:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E92903858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe2f.google.com with SMTP id h19so11681693vsv.13 for ; Sun, 12 Feb 2023 19:03:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=02aPmT7/GeIhAefjQc2Gm8e6loVsQMn/j7H1c/+XKYE=; b=dgrTogYTa2bMF1zACt1Csa+lVVyIG6OVlxVCQU3PmFg0RSvr7IzGevuIS6ybal7lsk GdLH3dls/ZHoGwYNdWJ2VnIQdyuQSpLYM/NNHiabikRKFtLY+kRGdC+d+Ycvz6pjlxhQ 413LVkDJQoq54XsS0WIgjYKFBgVlDMctxCQD6zKK9QEELDiRcfQM8PsMCbAaZhe1n8qn tyrXoetANLkZtFW2YhL7MRvYD+zgBuHBJ/w7Qf1++2z3uzn8Wq9OWsyE7vvCLbkFQG3b mYdxtl2pHapoJiEspfaZ5RdyJNsROwVMYZDV6U85GnrsiVtWCFRMGRbm30tzfs8fSaBs 7+yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=02aPmT7/GeIhAefjQc2Gm8e6loVsQMn/j7H1c/+XKYE=; b=BC4SvsyUTnWSEi0KmvYyWvIpVXvCJSn5EuYhRxrJ2kDwmmsZAw7qEwHusncNjzcPd4 m2a3Koq/UxA1sotzN+nYLycBc6PnAVFK13ptMHb6BSChPoiNVD465+u55em8QMOGovbj a4Z7P58VTaCj1FJCZK+7vYkyqyXmQN5dRpF3vzeCGA6+4jzudBoaUYVOnaP3lrktNvqN 5TFy3KFbfBc1GXoOCjyC9vMunQVc/BR3ImWuttIinugAXDEXrWY0SEnq8NlMgjJuEo6u e7XQdh3Mxs6ssO44lAoHaNEJSexzQuhgYlerGa+JE8q9nrrbfBbFpLFnNqi3fhWqsqKv wr0w== X-Gm-Message-State: AO0yUKUnUNZfue2AAbgtWk0DxW9+b/qXFQDeukaq5MMKIUh2OhlNVljI aLz70kIPL2rL51KAq1yGWV0cIR6+MWcYq+l0+1w= X-Google-Smtp-Source: AK7set+rf6kJlJJ370WujhtktpdEyNHU3gHXQEjPcqAdS7Xg9DVUgVSwXdeRr7w6n8fvRC7DoLrxorouHxTu15FTS5Y= X-Received: by 2002:a05:6102:559f:b0:411:a043:bb3f with SMTP id dc31-20020a056102559f00b00411a043bb3fmr4141503vsb.14.1676257416057; Sun, 12 Feb 2023 19:03:36 -0800 (PST) MIME-Version: 1.0 References: <20230212113359.18239-1-kito.cheng@sifive.com> In-Reply-To: From: Kito Cheng Date: Mon, 13 Feb 2023 11:03:24 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Handle vlenb correctly in unwinding To: juzhe.zhong@rivai.ai Cc: "kito.cheng" , gcc-patches , "jim.wilson.gcc" , palmer , andrew Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: committed :) On Sun, Feb 12, 2023 at 10:42 PM wrote: > > LGTM > > > > juzhe.zhong@rivai.ai > > From: Kito Cheng > Date: 2023-02-12 19:33 > To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; juzhe.zhong > CC: Kito Cheng > Subject: [PATCH] RISC-V: Handle vlenb correctly in unwinding > gcc/ChangeLog: > > * config/riscv/riscv.h (RISCV_DWARF_VLENB): New. > (DWARF_FRAME_REGISTERS): New. > (DWARF_REG_TO_UNWIND_COLUMN): New. > > libgcc/ChangeLog: > > * config.host (riscv*-*-*): Add config/riscv/value-unwind.h. > * config/riscv/value-unwind.h: New. > --- > gcc/config/riscv/riscv.h | 7 ++++++ > libgcc/config.host | 3 +++ > libgcc/config/riscv/value-unwind.h | 39 ++++++++++++++++++++++++++++++ > 3 files changed, 49 insertions(+) > create mode 100644 libgcc/config/riscv/value-unwind.h > > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 120faf17c06..5bc7f2f467d 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -1088,4 +1088,11 @@ extern void riscv_remove_unneeded_save_restore_calls (void); > #define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE) > +#define RISCV_DWARF_VLENB (4096 + 0xc22) > + > +#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 1 /* VLENB */) > + > +#define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \ > + ((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO) > + > #endif /* ! GCC_RISCV_H */ > diff --git a/libgcc/config.host b/libgcc/config.host > index 70d47e08e40..b9975de9023 100644 > --- a/libgcc/config.host > +++ b/libgcc/config.host > @@ -1559,6 +1559,9 @@ aarch64*-*-*) > # ILP32 needs an extra header for unwinding > tm_file="${tm_file} aarch64/value-unwind.h" > ;; > +riscv*-*-*) > + tm_file="${tm_file} riscv/value-unwind.h" > + ;; > esac > # Setup to build a shared libgcc for VxWorks when that was requested, > diff --git a/libgcc/config/riscv/value-unwind.h b/libgcc/config/riscv/value-unwind.h > new file mode 100644 > index 00000000000..d7efdc14e6f > --- /dev/null > +++ b/libgcc/config/riscv/value-unwind.h > @@ -0,0 +1,39 @@ > +/* Store register values as _Unwind_Word type in DWARF2 EH unwind context. > + Copyright (C) 2023 Free Software Foundation, Inc. > + > + This file is part of GCC. > + > + GCC is free software; you can redistribute it and/or modify it > + under the terms of the GNU General Public License as published > + by the Free Software Foundation; either version 3, or (at your > + option) any later version. > + > + GCC is distributed in the hope that it will be useful, but WITHOUT > + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY > + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public > + License for more details. > + > + Under Section 7 of GPL version 3, you are granted additional > + permissions described in the GCC Runtime Library Exception, version > + 3.1, as published by the Free Software Foundation. > + > + You should have received a copy of the GNU General Public License and > + a copy of the GCC Runtime Library Exception along with this program; > + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > + . */ > + > +/* Return the value of the VLENB register. This should only be > + called if we know this is an vector extension enabled RISC-V host. */ > +static inline long > +riscv_vlenb (void) > +{ > + register long vlenb asm ("a0"); > + /* 0xc2202573 == csrr a0, 0xc22 */ > + asm (".insn 0xc2202573" : "=r"(vlenb)); > + return vlenb; > +} > + > +/* Lazily provide a value for VLENB, so that we don't try to execute RVV > + instructions unless we know they're needed. */ > +#define DWARF_LAZY_REGISTER_VALUE(REGNO, VALUE) \ > + ((REGNO) == RISCV_DWARF_VLENB && ((*VALUE) = riscv_vlenb (), 1)) > -- > 2.37.2 > >