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From: Kito Cheng <kito.cheng@gmail.com>
To: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
Cc: "yanzhang.wang" <yanzhang.wang@intel.com>,
	gcc-patches <gcc-patches@gcc.gnu.org>,
	 "Kito.cheng" <kito.cheng@sifive.com>,
	"pan2.li" <pan2.li@intel.com>
Subject: Re: [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all
Date: Thu, 6 Apr 2023 22:59:24 +0800	[thread overview]
Message-ID: <CA+yXCZAPOy5ihSD=HPtJxgGAt4GFAHc+pV-UeioaQ+83k0noLQ@mail.gmail.com> (raw)
In-Reply-To: <D1C4FFFF72E1077B+2023040621470861967893@rivai.ai>

> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 2e91d019f6c..90c69b52bb4 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -43,6 +43,7 @@
> #include "optabs.h"
> #include "tm-constrs.h"
> #include "rtx-vector-builder.h"
> +#include "diagnostic-core.h"
> using namespace riscv_vector;
> @@ -724,4 +725,82 @@ gen_avl_for_scalar_move (rtx avl)
>      }
> }
> +/* Generate a sequence of instructions that zero registers specified by
> +   NEED_ZEROED_HARDREGS.  Return the ZEROED_HARDREGS that are actually
> +   zeroed.  */
> +static HARD_REG_SET
> +gpr_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)

Drop this - call default_zero_call_used_regs instead of build our own one.

> +{
> +  HARD_REG_SET zeroed_hardregs;
> +  CLEAR_HARD_REG_SET (zeroed_hardregs);
> +
> +  for (unsigned regno = GP_REG_FIRST; regno <= GP_REG_LAST; ++regno)
> +    {
> +      if (!TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
> + continue;
> +
> +      rtx reg = regno_reg_rtx[regno];
> +      machine_mode mode = GET_MODE (reg);
> +      emit_move_insn (reg, CONST0_RTX (mode));
> +
> +      SET_HARD_REG_BIT (zeroed_hardregs, regno);
> +    }
> +
> +  return zeroed_hardregs;
> +}
> +
> +static HARD_REG_SET
> +vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)

Plz move this into riscv.cc

> +{
> +  HARD_REG_SET zeroed_hardregs;
> +  CLEAR_HARD_REG_SET (zeroed_hardregs);
> +
> +  /* Find a register to hold vl.  */
> +  unsigned vl_regno = GP_REG_LAST + 1;

Use INVALID_REGNUM as sentinel value

> +  for (unsigned regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)

Start from `GP_REG_FIRST + 1`

> +    {
> +      /* If vl and avl both are x0, the existing vl is kept.  */
> +      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno) && regno != X0_REGNUM)

Then we don't need to check `regno != X0_REGNUM` here.

> + {
> +   vl_regno = regno;
> +   break;
> + }
> +    }
> +
> +  if (vl_regno > GP_REG_LAST)
> +    sorry ("can't allocate vl register for %qs on this target",
> +    "-fzero-call-used-regs");
> +
> +  rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX.  */
> +  for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno)
> +    {
> +      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
> + {
> +   rtx target = regno_reg_rtx[regno];
> +   machine_mode mode = GET_MODE (target);
> +   poly_uint16 nunits = GET_MODE_NUNITS (mode);
> +   machine_mode mask_mode = get_vector_mode (BImode, nunits).require ();
> +
> +   emit_vlmax_vsetvl (mode, vl);

You can add an variable to check vlmax_vsetvl is emitted or not, and
skip that if already emitted

e.g.

if (!emitted_vlmax_vsetvl)
  emit_vlmax_vsetvl (mode, vl);

emitted_vlmax_vsetvl = true;

Add a new function maybe named emit_hard_vlmax_vsetvl to prevent the
vsetvli instruction gone when optimization is enabled.
---
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 4611447ddde..5244e8dcbf0 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -159,6 +159,7 @@ bool check_builtin_call (location_t,
vec<location_t>, unsigned int,
 bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
 bool legitimize_move (rtx, rtx, machine_mode);
 void emit_vlmax_vsetvl (machine_mode, rtx);
+void emit_hard_vlmax_vsetvl (machine_mode, rtx);
 void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);
 void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
 void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 90c69b52bb4..6d34e3a2b6c 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -119,6 +119,20 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
          && IN_RANGE (INTVAL (elt), minval, maxval));
 }

+/* Emit a vlmax vsetvl instruction with side effect, this should be only used
+   when optimization is tune off or emit after vsetvl insertion pass.  */
+void
+emit_hard_vlmax_vsetvl (machine_mode vmode, rtx vl)
+{
+  unsigned int sew = get_sew (vmode);
+  enum vlmul_type vlmul = get_vlmul (vmode);
+  unsigned int ratio = calculate_ratio (sew, vlmul);
+
+  emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
+                        gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
+                        const0_rtx));
+}
+
 void
 emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
 {
@@ -127,9 +141,7 @@ emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
   unsigned int ratio = calculate_ratio (sew, vlmul);

   if (!optimize)
-    emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
-                          gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
-                          const0_rtx));
+    emit_hard_vlmax_vsetvl (vmode, vl);
   else
     emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio, Pmode)));
 }

---


> +   emit_vlmax_op (code_for_pred_mov (mode), target, CONST0_RTX (mode),
> + vl, mask_mode);
> +
> +   SET_HARD_REG_BIT (zeroed_hardregs, regno);
> + }
> +    }
> +
> +  return zeroed_hardregs;
> +}
> +
> +HARD_REG_SET
> +riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)

Plz move this into riscv.cc

> +{
> +  HARD_REG_SET zeroed_hardregs;
> +  CLEAR_HARD_REG_SET (zeroed_hardregs);
> +
> +  if (TARGET_VECTOR)
> +    zeroed_hardregs |= vector_zero_call_used_regs (need_zeroed_hardregs);
> +
> +  return zeroed_hardregs | gpr_zero_call_used_regs (need_zeroed_hardregs);

Call default_zero_call_used_regs here, e.g.

return zeroed_hardregs | default_zero_call_used_regs
(need_zeroed_hardregs & ~zeroed_hardregs);

Also one important reason is default_zero_call_used_regs also zero init all FRP.

> +}
> } // namespace riscv_vector
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 5f542932d13..e176f2d9f34 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -7317,6 +7317,12 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
> #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
> #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
> +namespace riscv_vector {
> +extern HARD_REG_SET riscv_zero_call_used_regs (HARD_REG_SET);
> +}
> +#undef TARGET_ZERO_CALL_USED_REGS
> +#define TARGET_ZERO_CALL_USED_REGS riscv_vector::riscv_zero_call_used_regs
> +
> struct gcc_target targetm = TARGET_INITIALIZER;
> #include "gt-riscv.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
> new file mode 100644
> index 00000000000..2d9dfeb9dc2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */
> +
> +void
> +foo (void)
> +{
> +}
> +
> +/* { dg-final { scan-assembler-not "li\t" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
> new file mode 100644
> index 00000000000..a53f034b5d5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
> @@ -0,0 +1,24 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -fzero-call-used-regs=all-gpr" } */

Add -march=rv64gc -mabi=lp64 to dg-options, otherwise it will failed
when default config is rv32e

Plz add one more test case with -march=rv64gcv -mabi=lp64 is work as well.

> +
> +void
> +foo (void)
> +{
> +}
> +
> +/* { dg-final { scan-assembler-not "vsetvli" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
> --
> 2.39.2
>
>

  reply	other threads:[~2023-04-06 14:59 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-06 13:34 yanzhang.wang
2023-04-06 13:47 ` juzhe.zhong
2023-04-06 14:59   ` Kito Cheng [this message]
2023-04-07  6:59 ` [PATCH v2] " yanzhang.wang
2023-04-07  7:07   ` Kito Cheng
2023-04-07 12:32 ` [PATCH v3] " yanzhang.wang
2023-04-08 18:39   ` Jeff Law
2023-04-10  2:21     ` Wang, Yanzhang
2023-04-10  3:11       ` Kito Cheng
2023-04-10 20:57         ` Jeff Law
2023-04-10  3:00 ` [PATCH v4] " yanzhang.wang
2023-04-11 11:37 ` [PATCH v5] " yanzhang.wang
2023-04-11 12:00   ` Wang, Yanzhang
2023-04-11 14:11     ` Kito Cheng

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