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From: Kito Cheng <kito.cheng@gmail.com>
To: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
Cc: "pan2.li" <pan2.li@intel.com>, gcc-patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH v1] RISC-V: Fix ICE for legitimize move on subreg const_poly_move
Date: Mon, 29 Apr 2024 14:37:06 +0800	[thread overview]
Message-ID: <CA+yXCZARfxBt-bN7uD=-NiAbRsf-=S6to3TjZPfXkVzr+wvuZQ@mail.gmail.com> (raw)
In-Reply-To: <3B41D6784D041B3E+202404281155358620832@rivai.ai>

> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 0519e0679ed..bad23ea487f 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2786,6 +2786,44 @@ riscv_v_adjust_scalable_frame (rtx target, poly_int64 offset, bool epilogue)
>    REG_NOTES (insn) = dwarf;
> }
> +/* Take care below subreg const_poly_int move:
> +
> +   1. (set (subreg:DI (reg:TI 237) 8)
> +    (subreg:DI (const_poly_int:TI [4, 2]) 8))
> +      =>
> +      (set (subreg:DI (reg:TI 237) 8)
> +    (const_int 0)) */
> +
> +static bool
> +riscv_legitimize_subreg_const_poly_move (machine_mode mode, rtx dest, rtx src)
> +{
> +  gcc_assert (SUBREG_P (src) && CONST_POLY_INT_P (SUBREG_REG (src)));
> +  gcc_assert (SUBREG_BYTE (src).is_constant ());
> +
> +  int byte_offset = SUBREG_BYTE (src).to_constant ();
> +  rtx const_poly = SUBREG_REG (src);
> +  machine_mode subreg_mode = GET_MODE (const_poly);
> +
> +  if (subreg_mode != TImode) /* Only TImode is needed for now.  */
> +    return false;
> +
> +  if (byte_offset == 8)
> +    { /* The const_poly_int cannot exceed int64, just set zero here.  */

{
 /* The const_poly_int cannot exceed int64, just set zero here.  */

New line for the comment.

> +      emit_move_insn (dest, CONST0_RTX (mode));
> +      return true;
> +    }
> +
> +  /* The below transform will be covered in somewhere else.
> +     Thus, ignore this here.
> +   1. (set (subreg:DI (reg:TI 237) 0)
> +    (subreg:DI (const_poly_int:TI [4, 2]) 0))
> +      =>
> +      (set (subreg:DI (reg:TI 237) 0)
> +    (const_poly_int:DI [4, 2])) */
> +
> +  return false;
> +}
> +
> /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
>     sequence that is valid.  */
> @@ -2839,6 +2877,11 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
> }
>        return true;
>      }
> +
> +  if (SUBREG_P (src) && CONST_POLY_INT_P (SUBREG_REG (src))
> +    && riscv_legitimize_subreg_const_poly_move (mode, dest, src))
> +    return true;
> +
>    /* Expand
>         (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
>       Expand this data movement instead of simply forbid it since
> --
> 2.34.1
>
>

  reply	other threads:[~2024-04-29  6:37 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-28  3:53 pan2.li
2024-04-28  3:55 ` juzhe.zhong
2024-04-29  6:37   ` Kito Cheng [this message]
2024-04-29  7:41     ` Li, Pan2
2024-04-29  7:40 ` [PATCH v2] RISC-V: Fix ICE for legitimize move on subreg const_poly_int [PR114885] pan2.li
2024-04-29  7:47   ` Kito Cheng
2024-04-29  7:53     ` Jakub Jelinek
2024-04-29  8:33       ` Li, Pan2

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