From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x929.google.com (mail-ua1-x929.google.com [IPv6:2607:f8b0:4864:20::929]) by sourceware.org (Postfix) with ESMTPS id 0AD06385B52C for ; Fri, 23 Dec 2022 05:42:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0AD06385B52C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x929.google.com with SMTP id c26so859817uak.5 for ; Thu, 22 Dec 2022 21:42:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=GfccNed7ztMYwp/IJZzS1JSTl0XV84pxXRirm4G4pDQ=; b=D4y/hd5tihXVZL+hTwSDnB1CjgM3BNVbcszjSehJ4mS/pSVMQINd/U9eKkzW4kla0v wHOTOj6iL8ZBd7lI7WNVRVRxvnpHHWChmI0QybsFtwsJ83AUiEfgPxqfAjOuCaRpESdj 1mkx8xgMokT/Ti9glObftvA0OHRjnFwuFDxSgm77/zrKadz/ipDiXP85rH4YXFD0N8Wu 99CKRnr8lLaT7vK4+jpsZf/khyL7Q2mODs5pFqVys6a3bs54FJU2qENYwFoB2VGYvqeY cZ2s4LmWK8HQCmdub9gRO9ndSI8U8lJE3cSxdvp18k6WYTwRGQOY1iEKKR7PTvFatkoR 7EOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=GfccNed7ztMYwp/IJZzS1JSTl0XV84pxXRirm4G4pDQ=; b=3+Jix0rLkyLj7Wb1P4JNMaCfNz3stoMNKduZ9GsyJJETdCVLddvuLcDbGyLAGyQpo3 X4HLrDjHj6Rk1ow53ohQKpIgqEBqWEouBWE2siHvkx0tjP2H4+2D3B+caPbG8CxGaw4c wv6FW49RPoYmEJqwbpzV/Ga6df8y+G8BlP7v2QhZvkkIWexi1M8ussxmyMDSgIoBsGyW LLNwn5dXD1r2RtFCayFS/UTvXNfsN4zE+ACWEgByTOqxWLA4k1z8VqFko5NHxL9aYoBY HaMlRo8jqrHF2nYh3TQ/TW1LjTnq/EFeEbeKQwHzKoUriAiwYOlLyQFnmnqKiLg0gPMj HEGQ== X-Gm-Message-State: AFqh2kqVYZ08FHZaMLeoyYiMeTx/3bE0fjqYnpPE5fvtRXFaljkLmOnJ MtMBI2yuAdYu0wNm9OZ190SoDvNFUXrvo0bwf9Y= X-Google-Smtp-Source: AMrXdXv+tm8SS7nAxPIDp8BxJocqquoUsTxKbv5vHBgDv3TRbIOaBi+itlkRJyS+aquWMICfVA0Mw37lsV8n+OJ3wJg= X-Received: by 2002:ab0:760d:0:b0:47b:95bb:54d3 with SMTP id o13-20020ab0760d000000b0047b95bb54d3mr728352uap.97.1671774169574; Thu, 22 Dec 2022 21:42:49 -0800 (PST) MIME-Version: 1.0 References: <20221223033306.264797-1-juzhe.zhong@rivai.ai> In-Reply-To: <20221223033306.264797-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Fri, 23 Dec 2022 13:42:38 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Fix vle constraints To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed, thanks :) On Fri, Dec 23, 2022 at 11:33 AM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/vector.md: Fix contraints. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/vle-constraint-1.c: New test. > > --- > gcc/config/riscv/vector.md | 16 +-- > .../riscv/rvv/base/vle-constraint-1.c | 109 ++++++++++++++++++ > 2 files changed, 117 insertions(+), 8 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 98b8f701c92..89810b183fc 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -636,18 +636,18 @@ > ;; 2. (const_vector:VNx1SF repeat [ > ;; (const_double:SF 0.0 [0x0.0p+0])]). > (define_insn_and_split "@pred_mov" > - [(set (match_operand:V 0 "nonimmediate_operand" "=vd, vr, m, vr, vr") > + [(set (match_operand:V 0 "nonimmediate_operand" "=vd, vr, m, vr, vr") > (if_then_else:V > (unspec: > - [(match_operand: 1 "vector_mask_operand" " vm, Wc1, vmWc1, Wc1, Wc1") > - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK") > - (match_operand 5 "const_int_operand" " i, i, i, i, i") > - (match_operand 6 "const_int_operand" " i, i, i, i, i") > - (match_operand 7 "const_int_operand" " i, i, i, i, i") > + [(match_operand: 1 "vector_mask_operand" "vmWc1, vmWc1, vmWc1, Wc1, Wc1") > + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK") > + (match_operand 5 "const_int_operand" " i, i, i, i, i") > + (match_operand 6 "const_int_operand" " i, i, i, i, i") > + (match_operand 7 "const_int_operand" " i, i, i, i, i") > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > - (match_operand:V 3 "vector_move_operand" " m, m, vr, vr, viWc0") > - (match_operand:V 2 "vector_merge_operand" " 0, vu, vu0, vu0, vu0")))] > + (match_operand:V 3 "vector_move_operand" " m, m, vr, vr, viWc0") > + (match_operand:V 2 "vector_merge_operand" " 0, vu, vu0, vu0, vu0")))] > "TARGET_VECTOR" > "@ > vle.v\t%0,%3%p1 > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c > new file mode 100644 > index 00000000000..b7cf98bfd9f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c > @@ -0,0 +1,109 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "riscv_vector.h" > + > +/* > +** f1: > +** vsetvli\tzero,4,e32,m1,tu,ma > +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) > +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) > +** vse32\.v\tv[0-9]+,0\([a-x0-9]+\) > +** ret > +*/ > +void f1 (float * in, float *out) > +{ > + vfloat32m1_t v = __riscv_vle32_v_f32m1 (in, 4); > + vfloat32m1_t v2 = __riscv_vle32_v_f32m1_tu (v, in, 4); > + __riscv_vse32_v_f32m1 (out, v2, 4); > +} > + > +/* > +** f2: > +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma > +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) > +** vsetvli\tzero,4,e32,m1,ta,ma > +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t > +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) > +** ret > +*/ > +void f2 (float * in, float *out) > +{ > + vbool32_t mask = *(vbool32_t*)in; > + asm volatile ("":::"memory"); > + vfloat32m1_t v = __riscv_vle32_v_f32m1 (in, 4); > + vfloat32m1_t v2 = __riscv_vle32_v_f32m1_m (mask, in, 4); > + __riscv_vse32_v_f32m1 (out, v2, 4); > +} > + > +/* > +** f3: > +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma > +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) > +** vsetvli\tzero,4,e32,m1,tu,mu > +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) > +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t > +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) > +** ret > +*/ > +void f3 (float * in, float *out) > +{ > + vbool32_t mask = *(vbool32_t*)in; > + asm volatile ("":::"memory"); > + vfloat32m1_t v = __riscv_vle32_v_f32m1 (in, 4); > + vfloat32m1_t v2 = __riscv_vle32_v_f32m1_tumu (mask, v, in, 4); > + __riscv_vse32_v_f32m1 (out, v2, 4); > +} > + > +/* > +** f4: > +** vsetvli\tzero,4,e8,mf8,tu,ma > +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) > +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) > +** vse8\.v\tv[0-9]+,0\([a-x0-9]+\) > +** ret > +*/ > +void f4 (int8_t * in, int8_t *out) > +{ > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in, 4); > + __riscv_vse8_v_i8mf8 (out, v2, 4); > +} > + > +/* > +** f5: > +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma > +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) > +** vsetvli\tzero,4,e8,mf8,ta,ma > +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t > +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) > +** ret > +*/ > +void f5 (int8_t * in, int8_t *out) > +{ > + vbool64_t mask = *(vbool64_t*)in; > + asm volatile ("":::"memory"); > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_m (mask, in, 4); > + __riscv_vse8_v_i8mf8 (out, v2, 4); > +} > + > +/* > +** f6: > +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma > +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) > +** vsetvli\tzero,4,e8,mf8,tu,mu > +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) > +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t > +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) > +** ret > +*/ > +void f6 (int8_t * in, int8_t *out) > +{ > + vbool64_t mask = *(vbool64_t*)in; > + asm volatile ("":::"memory"); > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in, 4); > + __riscv_vse8_v_i8mf8 (out, v2, 4); > +} > -- > 2.36.3 >