From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa2f.google.com (mail-vk1-xa2f.google.com [IPv6:2607:f8b0:4864:20::a2f]) by sourceware.org (Postfix) with ESMTPS id 1AD443858D20 for ; Mon, 12 Jun 2023 12:48:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1AD443858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa2f.google.com with SMTP id 71dfb90a1353d-464f8a20c05so1151653e0c.1 for ; Mon, 12 Jun 2023 05:48:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686574094; x=1689166094; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=msC3PLxZJHXaj0W7MZYjN8eOlG1VtlTwWNNUgvbqOZE=; b=l2nRta8kXJYl4WSbRGXyniE06r/H/Q/sQHBsVffaLZatHk17KX/nkHGO6BV2CV2BrB QR3DlIL3KoalotAH0gT+sYjm8hrjNKDZP3bxmIY77meg6C8/zwOnDWUEo7A3xRYHi7dP GQSlYC4rcZ+af4H5Wu6zDN6sTEr7M4id4hE6bSzzAiVIzDXMwOVAx+QA38w0inclOeCl DAY5Ht2j4Rc/5XoE+rOVy2wOXMwQrryD1vkEzA+8zgmTpbyd94DI2XIuFu7jMz2304mf cvXuidZecspilQ6GTn1YJAM7j//ibj7IvWJNdPT3OeinTInag3juG42LZLfO6s44CSXs u2UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686574094; x=1689166094; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=msC3PLxZJHXaj0W7MZYjN8eOlG1VtlTwWNNUgvbqOZE=; b=F0hqNGvGkwoH2zai1TqYQPRtcS4Be/cct8Yo2UgmzUNrLQmeEEz9KvUnQKlHdHlKO9 JVvTyl+UKjf4cPqVMDrzjr0z/xANrlkDOAcKeHMJQ7cfaSgikDhak8ZClQ6aOAboL0oJ v7BugoFpUEW+1Uo6QpBGmnBA/yKJsyl05t3YyKpwTiimkiH05ZlWHfoabJtrFHrOq8q4 WekWSRNPxe2jiseHRabMy2W4un2XSA1Jej4500fzJL4i97tRdBkjNnqYRzTzL3kL24x5 w1sU+nnXMgAfxXZR0qlbPCsMPQX7eVHisM2LM6InY0U+mQJHnlzSzXqZU/j/HMU9KN22 6sxw== X-Gm-Message-State: AC+VfDwkvr71rlDh++i4NOIxcb6txd8UUryMuBcxFE8gJBmi132o/Q/F ef5riEoM2KoZtZ/0au/CQDpoA41WvAaHi8Sq/1g= X-Google-Smtp-Source: ACHHUZ4OtbckHEccEu8WoVfLf5XcvcJisU42X2TQBisP64/63Tv9usgW2CeKiS96LCUVpD6cl2R8ocSRhZG8iP3JKis= X-Received: by 2002:a67:ff0c:0:b0:43a:3295:dddf with SMTP id v12-20020a67ff0c000000b0043a3295dddfmr2887567vsp.9.1686574094195; Mon, 12 Jun 2023 05:48:14 -0700 (PDT) MIME-Version: 1.0 References: <20230612074024.454116-1-pan2.li@intel.com> <06C16C6DDACA91CF+202306121542084895571@rivai.ai> In-Reply-To: <06C16C6DDACA91CF+202306121542084895571@rivai.ai> From: Kito Cheng Date: Mon, 12 Jun 2023 20:48:03 +0800 Message-ID: Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API To: "juzhe.zhong@rivai.ai" Cc: "pan2.li" , gcc-patches , Robin Dapp , jeffreyalaw , "yanzhang.wang" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: lgtm On Mon, Jun 12, 2023 at 3:43=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > LGTM > > > > juzhe.zhong@rivai.ai > > From: pan2.li > Date: 2023-06-12 15:40 > To: gcc-patches > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.che= ng > Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API > From: Pan Li > > This patch support the intrinsic API of FP16 ZVFHMIN vget/vset. From > the user's perspective, it is reasonable to do some get/set operations > for the vfloat16*_t types when only ZVFHMIN is enabled. > > Signed-off-by: Pan Li > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins-types.def > (vfloat16m1_t): Add type to lmul1 ops. > (vfloat16m2_t): Likewise. > (vfloat16m4_t): Likewise. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new test cases. > * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Likewise. > --- > .../riscv/riscv-vector-builtins-types.def | 3 ++ > .../riscv/rvv/base/zvfh-over-zvfhmin.c | 15 +++++++-- > .../riscv/rvv/base/zvfhmin-intrinsic.c | 32 ++++++++++++++----- > 3 files changed, 40 insertions(+), 10 deletions(-) > > diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/confi= g/riscv/riscv-vector-builtins-types.def > index db8e61fea6a..4926bd8a2d2 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-types.def > +++ b/gcc/config/riscv/riscv-vector-builtins-types.def > @@ -1091,6 +1091,7 @@ DEF_RVV_LMUL1_OPS (vuint8m1_t, 0) > DEF_RVV_LMUL1_OPS (vuint16m1_t, 0) > DEF_RVV_LMUL1_OPS (vuint32m1_t, 0) > DEF_RVV_LMUL1_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) > +DEF_RVV_LMUL1_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) > DEF_RVV_LMUL1_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32) > DEF_RVV_LMUL1_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64) > @@ -1102,6 +1103,7 @@ DEF_RVV_LMUL2_OPS (vuint8m2_t, 0) > DEF_RVV_LMUL2_OPS (vuint16m2_t, 0) > DEF_RVV_LMUL2_OPS (vuint32m2_t, 0) > DEF_RVV_LMUL2_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) > +DEF_RVV_LMUL2_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16) > DEF_RVV_LMUL2_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32) > DEF_RVV_LMUL2_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64) > @@ -1113,6 +1115,7 @@ DEF_RVV_LMUL4_OPS (vuint8m4_t, 0) > DEF_RVV_LMUL4_OPS (vuint16m4_t, 0) > DEF_RVV_LMUL4_OPS (vuint32m4_t, 0) > DEF_RVV_LMUL4_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) > +DEF_RVV_LMUL4_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16) > DEF_RVV_LMUL4_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32) > DEF_RVV_LMUL4_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64) > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c = b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c > index c3ed4191a36..1d82cc8de2d 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c > @@ -61,6 +61,14 @@ vfloat16m8_t test_vundefined_f16m8() { > return __riscv_vundefined_f16m8(); > } > +vfloat16m2_t test_vset_v_f16m1_f16m2(vfloat16m2_t dest, size_t index, vf= loat16m1_t val) { > + return __riscv_vset_v_f16m1_f16m2(dest, 0, val); > +} > + > +vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) { > + return __riscv_vget_v_f16m8_f16m4(src, 0); > +} > + > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,= \s*mf4,\s*t[au],\s*m[au]} 3 } } */ > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,= \s*m4,\s*t[au],\s*m[au]} 2 } } */ > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,= \s*m8,\s*t[au],\s*m[au]} 1 } } */ > @@ -71,7 +79,10 @@ vfloat16m8_t test_vundefined_f16m8() { > /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]= +} 2 } } */ > /* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)= } 7 } } */ > /* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 6 } } */ > -/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0= -9]+\)} 1 } } */ > +/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0= -9]+\)} 1 } } */ > +/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0= -9]+\)} 1 } } */ > +/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0= -9]+\)} 3 } } */ > /* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-= 9]+\)} 1 } } */ > -/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 1 } } */ > +/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 1 } } */ > +/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 3 } } */ > /* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+= \)} 5 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c = b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > index 8d39a2ed4c2..1026b3f82f1 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > @@ -165,6 +165,22 @@ vfloat16m8_t test_vundefined_f16m8() { > return __riscv_vundefined_f16m8(); > } > +vfloat16m2_t test_vset_v_f16m1_f16m2(vfloat16m2_t dest, size_t index, vf= loat16m1_t val) { > + return __riscv_vset_v_f16m1_f16m2(dest, 0, val); > +} > + > +vfloat16m8_t test_vset_v_f16m4_f16m8(vfloat16m8_t dest, size_t index, vf= loat16m4_t val) { > + return __riscv_vset_v_f16m4_f16m8(dest, 0, val); > +} > + > +vfloat16m1_t test_vget_v_f16m2_f16m1(vfloat16m2_t src, size_t index) { > + return __riscv_vget_v_f16m2_f16m1(src, 0); > +} > + > +vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) { > + return __riscv_vget_v_f16m8_f16m4(src, 0); > +} > + > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,= \s*mf4,\s*t[au],\s*m[au]} 3 } } */ > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,= \s*mf2,\s*t[au],\s*m[au]} 2 } } */ > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,= \s*m1,\s*t[au],\s*m[au]} 2 } } */ > @@ -180,11 +196,11 @@ vfloat16m8_t test_vundefined_f16m8() { > /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]= +} 5 } } */ > /* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 20 } } */ > /* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 15 } } */ > -/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0= -9]+\)} 3 } } */ > -/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0= -9]+\)} 3 } } */ > -/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0= -9]+\)} 4 } } */ > -/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0= -9]+\)} 3 } } */ > -/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 4 } } */ > -/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 4 } } */ > -/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 4 } } */ > -/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 12 } } */ > +/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0= -9]+\)} 5 } } */ > +/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0= -9]+\)} 4 } } */ > +/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0= -9]+\)} 5 } } */ > +/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0= -9]+\)} 5 } } */ > +/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 5 } } */ > +/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 5 } } */ > +/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 5 } } */ > +/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]= +\)} 13 } } */ > -- > 2.34.1 > >