From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1130.google.com (mail-yw1-x1130.google.com [IPv6:2607:f8b0:4864:20::1130]) by sourceware.org (Postfix) with ESMTPS id DA009385841A for ; Thu, 31 Aug 2023 13:10:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DA009385841A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x1130.google.com with SMTP id 00721157ae682-58d9ba95c78so9474757b3.1 for ; Thu, 31 Aug 2023 06:10:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693487400; x=1694092200; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=rn0iSWQD4dIClYoyhx7a0Oe8dVEaUPgJ/+0Wuh+jo/c=; b=FMRR0mVoBf0wuOOj1sNnFjghAdyHWO6Arg49sJgUo3HGDEySYyPOePMZHdKAo+H/HO gK24ELYArFf6Hyj0ZRW5pY/SBTgQcDDLeyNJpjgDcyibiK/4Ky2lxmncOI8dHTUL+H13 0odOhOXsRzMcAiCOIZFEW7EuWO6SWvtojoj/EVhuLApDXikhqh9cS3xr2/1LcyIDMg+p UT8TTbO4CrsdUm7id60qE+FMTmYOMDsJzlPeQZNbN9hSJjdALf8PxOVFzEeIN4nZptNT qsH2hFCxgvbXXmuTHcYLGKxTQMiY17ZL6elcKjRKyEd1jdw9/ZOGsQAc1A4kQLwL8ngb 8Gdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693487400; x=1694092200; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rn0iSWQD4dIClYoyhx7a0Oe8dVEaUPgJ/+0Wuh+jo/c=; b=leNdkjWMXvLYh9r4i+CtfbNlAToFYoshstLRyXuZRxx/urE2qsilTaOonPQ0M8dAx+ +PYsUkDSDSTthQtuWr2Ea4KP8G45Bq00g/Lf7btTnS754IMr8KeKM77Nv4HNuECS/nn+ QTRWmdKVZHMDn68FKAXRhPTvMg3MLxNHGtquhDc+rufdWARH1Vn4QbgTlM7qx5kPH4+V wS3ynL+E5U3+bKO/mIjSPie7ePVc+/0oog7yrTMHVss/tv6Y6SPqLYqwbCqjfHiza3Mt sF+ymoWXgIRUzTt0I8mjnzGfWxvHsJqurlDqoItWg+EpiZWVMkFzMylVl7C/C0x8g6AT uKYQ== X-Gm-Message-State: AOJu0YzRP8ILefvGEWC3MITPoI4L8NJSWsgzGZf7XBsexGTSBsNUM+Qz 0605L0+SNyLHwXO08rYu5jOlPla+XByIwX9zJKI= X-Google-Smtp-Source: AGHT+IETse2Ky/eRzETT35w1YtxdQ1qIOOxM40vphE1whpt3P7hIQRt7+0UEC+bce4d4sWvXjdk/1gfA3/M1hECBFkI= X-Received: by 2002:a81:7703:0:b0:592:608b:b9f7 with SMTP id s3-20020a817703000000b00592608bb9f7mr4818986ywc.35.1693487399994; Thu, 31 Aug 2023 06:09:59 -0700 (PDT) MIME-Version: 1.0 References: <20230824044907.4078472-1-pan2.li@intel.com> In-Reply-To: <20230824044907.4078472-1-pan2.li@intel.com> From: Kito Cheng Date: Thu, 31 Aug 2023 21:09:48 +0800 Message-ID: Subject: Re: [PATCH v1] RISC-V: Support rounding mode for VFMADD/VFMACC autovec To: pan2.li@intel.com Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, yanzhang.wang@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM On Thu, Aug 24, 2023 at 12:49=E2=80=AFPM Pan Li via Gcc-patches wrote: > > From: Pan Li > > There will be a case like below for intrinsic and autovec combination > > vfadd RTZ <- intrinisc static rounding > vfmadd <- autovec/autovec-opt > > The autovec generated vfmadd should take DYN mode, and the > frm must be restored before the vfmadd insn. This patch > would like to fix this issue by: > > * Add the frm operand to the vfmadd/vfmacc autovec/autovec-opt pattern. > * Set the frm_mode attr to DYN. > > Thus, the frm flow when combine autovec and intrinsic should be. > > +------------ > | frrm a5 > | ... > | fsrmi 4 > | vfadd <- intrinsic static rounding. > | ... > | fsrm a5 > | vfmadd <- autovec/autovec-opt > | ... > +------------ > > However, we leverage unspec instead of use to consume the FRM register > because there are some restrictions from the combine pass. Some code > path of try_combine may require the XVECLEN(pat, 0) =3D=3D 2 for the > recog_for_combine, and add new use will make the XVECLEN(pat, 0) =3D=3D 3 > and result in the vfwmacc optimization failure. For example, in the > test widen-complicate-5.c and widen-8.c > > Finally, there will be other fma cases and they will be covered in > the underlying patches. > > Signed-off-by: Pan Li > Co-Authored-By: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmadd/vfmacc. > * config/riscv/autovec.md: Ditto. > * config/riscv/vector-iterators.md: Add UNSPEC_VFFMA. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: New test= . > --- > gcc/config/riscv/autovec-opt.md | 32 ++++--- > gcc/config/riscv/autovec.md | 26 +++--- > gcc/config/riscv/vector-iterators.md | 2 + > .../rvv/base/float-point-frm-autovec-1.c | 88 +++++++++++++++++++ > 4 files changed, 125 insertions(+), 23 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-f= rm-autovec-1.c > > diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-o= pt.md > index 99b609a99d9..4b07e80ad95 100644 > --- a/gcc/config/riscv/autovec-opt.md > +++ b/gcc/config/riscv/autovec-opt.md > @@ -459,12 +459,14 @@ (define_insn_and_split "*pred_single_widen_mul" > ;; vect__13.182_33 =3D .FMA (vect__11.180_35, vect__8.176_40, vect__4.17= 2_45); > (define_insn_and_split "*double_widen_fma" > [(set (match_operand:VWEXTF 0 "register_operand") > - (fma:VWEXTF > - (float_extend:VWEXTF > - (match_operand: 2 "register_operand")) > - (float_extend:VWEXTF > - (match_operand: 3 "register_operand")) > - (match_operand:VWEXTF 1 "register_operand")))] > + (unspec:VWEXTF > + [(fma:VWEXTF > + (float_extend:VWEXTF > + (match_operand: 2 "register_operand")) > + (float_extend:VWEXTF > + (match_operand: 3 "register_operand")) > + (match_operand:VWEXTF 1 "register_operand")) > + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] > "TARGET_VECTOR && can_create_pseudo_p ()" > "#" > "&& 1" > @@ -475,16 +477,19 @@ (define_insn_and_split "*double_widen_fma" > DONE; > } > [(set_attr "type" "vfwmuladd") > - (set_attr "mode" "")]) > + (set_attr "mode" "") > + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) > > ;; This helps to match ext + fma. > (define_insn_and_split "*single_widen_fma" > [(set (match_operand:VWEXTF 0 "register_operand") > - (fma:VWEXTF > - (float_extend:VWEXTF > - (match_operand: 2 "register_operand")) > - (match_operand:VWEXTF 3 "register_operand") > - (match_operand:VWEXTF 1 "register_operand")))] > + (unspec:VWEXTF > + [(fma:VWEXTF > + (float_extend:VWEXTF > + (match_operand: 2 "register_operand")) > + (match_operand:VWEXTF 3 "register_operand") > + (match_operand:VWEXTF 1 "register_operand")) > + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] > "TARGET_VECTOR && can_create_pseudo_p ()" > "#" > "&& 1" > @@ -501,7 +506,8 @@ (define_insn_and_split "*single_widen_fma" > DONE; > } > [(set_attr "type" "vfwmuladd") > - (set_attr "mode" "")]) > + (set_attr "mode" "") > + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) > > ;; ---------------------------------------------------------------------= ---- > ;; ---- [FP] VFWNMSAC > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index acca4c22b90..4894986d2a5 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -1126,22 +1126,27 @@ (define_insn_and_split "*fnma" > (define_expand "fma4" > [(parallel > [(set (match_operand:VF 0 "register_operand") > - (fma:VF > - (match_operand:VF 1 "register_operand") > - (match_operand:VF 2 "register_operand") > - (match_operand:VF 3 "register_operand"))) > + (unspec:VF > + [(fma:VF > + (match_operand:VF 1 "register_operand") > + (match_operand:VF 2 "register_operand") > + (match_operand:VF 3 "register_operand")) > + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) > (clobber (match_dup 4))])] > "TARGET_VECTOR" > { > operands[4] =3D gen_reg_rtx (Pmode); > - }) > + } > + [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) > > (define_insn_and_split "*fma" > [(set (match_operand:VF 0 "register_operand" "=3Dvr, vr, ?&vr") > - (fma:VF > - (match_operand:VF 1 "register_operand" " %0, vr, vr") > - (match_operand:VF 2 "register_operand" " vr, vr, vr") > - (match_operand:VF 3 "register_operand" " vr, 0, vr"))) > + (unspec:VF > + [(fma:VF > + (match_operand:VF 1 "register_operand" " %0, vr, vr") > + (match_operand:VF 2 "register_operand" " vr, vr, vr") > + (match_operand:VF 3 "register_operand" " vr, 0, vr")) > + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) > (clobber (match_operand:P 4 "register_operand" "=3Dr,r,r"))] > "TARGET_VECTOR" > "#" > @@ -1155,7 +1160,8 @@ (define_insn_and_split "*fma" > DONE; > } > [(set_attr "type" "vfmuladd") > - (set_attr "mode" "")]) > + (set_attr "mode" "") > + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) > > ;; ---------------------------------------------------------------------= ---- > ;; ---- [FP] VFNMSAC and VFNMSUB > diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vect= or-iterators.md > index 4023a038fe9..9b2fb135bdd 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -81,6 +81,8 @@ (define_c_enum "unspec" [ > UNSPEC_VCOMPRESS > UNSPEC_VLEFF > UNSPEC_MODIFY_VL > + > + UNSPEC_VFFMA > ]) > > (define_c_enum "unspecv" [ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-auto= vec-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1= .c > new file mode 100644 > index 00000000000..f4f17a306d5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c > @@ -0,0 +1,88 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv --param=3Driscv-autovec-preference=3Df= ixed-vlmax -ffast-math -mabi=3Dlp64 -O3 -Wno-psabi" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "riscv_vector.h" > + > +/* > +**test_1: > +** ... > +** frrm\t[axt][0-9]+ > +** ... > +** fsrmi\t1 > +** ... > +** vfsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrm\t[axt][0-9]+ > +** ... > +** vfmadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** ret > +*/ > +void > +test_1 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t= vl, > + double *in1, double *in2, double *out) > +{ > + *op_out =3D __riscv_vfsub_vv_f32m1_rm (op1, op2, 1, vl); > + > + for (int i =3D 0; i < 4; ++i) > + out[i] +=3D in1[i] * in2[i]; > +} > + > +/* > +**test_2: > +** ... > +** frrm\t[axt][0-9]+ > +** ... > +** fsrmi\t1 > +** ... > +** vfsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrm\t[axt][0-9]+ > +** ... > +** vfmadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrmi\t4 > +** ... > +** vfsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrm\t[axt][0-9]+ > +** ... > +** ret > +*/ > +void > +test_2 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t= vl, > + double *in1, double *in2, double *out) > +{ > + op2 =3D __riscv_vfsub_vv_f32m1_rm (op1, op2, 1, vl); > + > + for (int i =3D 0; i < 4; ++i) > + out[i] =3D out[i] * in1[i] + in2[i]; > + > + *op_out =3D __riscv_vfsub_vv_f32m1_rm (op1, op2, 4, vl); > +} > + > +/* > +**test_3: > +** ... > +** frrm\t[axt][0-9]+ > +** ... > +** vfmadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrmi\t4 > +** ... > +** vfsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+ > +** ... > +** fsrm\t[axt][0-9]+ > +** ... > +** ret > +*/ > +void > +test_3 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t= vl, > + double *in1, double *in2, double *in3, double *out) > +{ > + for (int i =3D 0; i < 4; ++i) > + out[i] =3D in1[i] + in2[i] * out[i]; > + > + *op_out =3D __riscv_vfsub_vv_f32m1_rm (op1, op2, 4, vl); > +} > -- > 2.34.1 >