From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x936.google.com (mail-ua1-x936.google.com [IPv6:2607:f8b0:4864:20::936]) by sourceware.org (Postfix) with ESMTPS id 160EF3858D1E for ; Fri, 9 Jun 2023 08:28:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 160EF3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x936.google.com with SMTP id a1e0cc1a2514c-789c56ead4fso591986241.1 for ; Fri, 09 Jun 2023 01:28:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686299307; x=1688891307; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=+ugWnyJ/33AZs6BaWi5sZAW8Ydn1s223u4852XcPLX0=; b=epvPnpDNlzIoIZYVVPeEOzCq74s9sO3c8RjEGaOITW9mfcn0A84BpzMpFtuxINED6u 09c2Zc7ZipRc9bu2ZY4dnqKCZZDY1QBQwaZBNS7iRH/SBHMdNc3ZmztC5yKIP8LWfd4S /6yfFlnQJhc+kWVIaPA2ki4TQzQlANUpvkMU9J8F8lG0q241uIG7ygCeQCDtthcigYpA PfPGRFchUtGyW3fMHRsDlrk1zQf/YVJ5f77pUqxMVVIKo2KgIzhFexu668gHmVSm9Qha THLuQBPwXV6ZbIE6MzwXISbkMKD9Ej2KDSIKp+9bhLfJXos62C5nyc46MiKvtcYOigmK MqXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686299307; x=1688891307; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+ugWnyJ/33AZs6BaWi5sZAW8Ydn1s223u4852XcPLX0=; b=CIvUDMvsNM56G4zrO4dvmINMqSNtYyYDdpgpgHocwQSfPfZBtQo1o76LUOnvMgrbao kxVTHJMGTtY/GzVC82SgeYKjQO/KXIOow1FaLFwAIwzLQQO2QP80uGHP5yNDdkYimZhw OzpdpY0OKFbxNfKOsEHJz/m8StUFI0lmznFLS+gjCQpd847sifnvFAUbDdNxEXRlMf0T TDK4HK6VHyLS0ZUdGhGJ3SBDrIB+oDAKQjoeg/DYJsqNZlwxA7jSzfA7kl8tOVFJIykY 7++bD0vKxmDMnJPFAPcKJuPF0g4yl48uKsjI/ixHC6md7usE6BxCo0tX+3SJOBVrXHB6 ORFQ== X-Gm-Message-State: AC+VfDwR0bHIN+3+cZ8BPdEwZW5u+nU4S6J9b11LmKMW3qYClXTYIOqg Jf6CnzalfKDa0G6LEMtBmCcXaOgQjTFc55dLMYXF1u0d X-Google-Smtp-Source: ACHHUZ5Bf4tOYbiZi2Ig53aToUy8IXdvr72KE/OIjt1OrfdhUqLYNCzGfS54wJhfz+hFBqolQSVTcxYTmUoV+M+deZM= X-Received: by 2002:a67:eb4c:0:b0:437:e5ce:7e8f with SMTP id x12-20020a67eb4c000000b00437e5ce7e8fmr488020vso.4.1686299307151; Fri, 09 Jun 2023 01:28:27 -0700 (PDT) MIME-Version: 1.0 References: <20230606123646.1553843-1-pan2.li@intel.com> <20230609070709.2087327-1-pan2.li@intel.com> <250067E6A648BD84+20230609151447008113141@rivai.ai> In-Reply-To: <250067E6A648BD84+20230609151447008113141@rivai.ai> From: Kito Cheng Date: Fri, 9 Jun 2023 16:28:15 +0800 Message-ID: Subject: Re: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. To: "juzhe.zhong@rivai.ai" Cc: "pan2.li" , gcc-patches , Robin Dapp , jeffreyalaw , "yanzhang.wang" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: lgtm too, thanks :) On Fri, Jun 9, 2023 at 3:15=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > LGTM. > > > > juzhe.zhong@rivai.ai > > From: pan2.li > Date: 2023-06-09 15:07 > To: gcc-patches > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.che= ng > Subject: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. > From: Pan Li > > This patch would like to refactor the requirement of both the ZVFH > and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the > iterators of RVV. And then the ZVFH will leverage one define attr as > the gate for FP16 supported or not. > > Please note the ZVFH will cover the ZVFHMIN instructions. This patch > add one test for this. > > Signed-off-by: Pan Li > Co-Authored by: Juzhe-Zhong > Co-Authored by: Kito Cheng > > gcc/ChangeLog: > > * config/riscv/riscv.md (enabled): Move to another place, and > add fp_vector_disabled to the cond. > (fp_vector_disabled): New attr defined for disabling fp. > * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test > for ZVFHMIN. > --- > gcc/config/riscv/riscv.md | 39 ++++++++++++++++--- > gcc/config/riscv/vector-iterators.md | 23 ++++++----- > .../riscv/rvv/base/zvfhmin-intrinsic.c | 15 ++++++- > 3 files changed, 59 insertions(+), 18 deletions(-) > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 38b8fba2a53..d8e935cb934 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -239,12 +239,6 @@ (define_attr "ext_enabled" "no,yes" > ] > (const_string "no"))) > -;; Attribute to control enable or disable instructions. > -(define_attr "enabled" "no,yes" > - (cond [(eq_attr "ext_enabled" "no") > - (const_string "no")] > - (const_string "yes"))) > - > ;; Classification of each insn. > ;; branch conditional branch > ;; jump unconditional jump > @@ -434,6 +428,39 @@ (define_attr "type" > (eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")] > (const_string "unknown"))) > +;; True if the float point vector is disabled. > +(define_attr "fp_vector_disabled" "no,yes" > + (cond [ > + (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv, > + vfwalu,vfwmul,vfmuladd,vfwmuladd, > + vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp, > + vfclass,vfmerge, > + vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof, > + vfredo,vfredu,vfwredo,vfwredu, > + vfslide1up,vfslide1down") > + (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64= HF") > + (match_test "!TARGET_ZVFH"))) > + (const_string "yes") > + > + ;; The mode records as QI for the FP16 <=3D> INT8 instruction. > + (and (eq_attr "type" "vfncvtftoi,vfwcvtitof") > + (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64= QI") > + (match_test "!TARGET_ZVFH"))) > + (const_string "yes") > + ] > + (const_string "no"))) > + > +;; Attribute to control enable or disable instructions. > +(define_attr "enabled" "no,yes" > + (cond [ > + (eq_attr "ext_enabled" "no") > + (const_string "no") > + > + (eq_attr "fp_vector_disabled" "yes") > + (const_string "no") > + ] > + (const_string "yes"))) > + > ;; Length of instruction in bytes. > (define_attr "length" "" > (cond [ > diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vect= or-iterators.md > index f4946d84449..234b712bc9d 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [ > (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TAR= GET_VECTOR_ELEN_64") > (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx= 16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >=3D 128") > - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") > - (VNx2HF "TARGET_VECTOR_ELEN_FP_16") > - (VNx4HF "TARGET_VECTOR_ELEN_FP_16") > + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN =3D=3D 32") > + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN =3D=3D 64") > (VNx8HF "TARGET_VECTOR_ELEN_FP_16") > (VNx16HF "TARGET_VECTOR_ELEN_FP_16") > (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [ > (define_mode_iterator V_FRACT [ > (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32"= ) (VNx8QI "TARGET_MIN_VLEN >=3D 128") > (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4= HI "TARGET_MIN_VLEN >=3D 128") > - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4= HF "TARGET_MIN_VLEN >=3D 128") > + > + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") > + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >=3D 128") > + > (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARG= ET_MIN_VLEN >=3D 128") > (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MI= N_VLEN < 128") > (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >=3D 128") > @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [ > ]) > (define_mode_iterator VWEXTF [ > - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") > - (VNx2SF "TARGET_VECTOR_ELEN_FP_32") > - (VNx4SF "TARGET_VECTOR_ELEN_FP_32") > - (VNx8SF "TARGET_VECTOR_ELEN_FP_32") > - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") > - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >=3D 128") > + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGE= T_MIN_VLEN < 128") > + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") > + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") > + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") > + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARG= ET_MIN_VLEN > 32") > + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARG= ET_MIN_VLEN >=3D 128") > (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") > (VNx2DF "TARGET_VECTOR_ELEN_FP_64") > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c = b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > index 0923b6bc4d2..f1a29b639e0 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c > @@ -3,6 +3,8 @@ > #include "riscv_vector.h" > +typedef _Float16 float16_t; > + > vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) { > return __riscv_vfncvt_f_f_w_f16mf4(src, vl); > } > @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src= , size_t vl) { > return __riscv_vfwcvt_f_f_v_f32m8(src, vl); > } > -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16= ,\s*mf4,\s*t[au],\s*m[au]} 2 } } */ > +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) { > + return __riscv_vle16_v_f16mf4(base, vl); > +} > + > +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) { > + return __riscv_vle16_v_f16m8(base, vl); > +} > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16= ,\s*mf4,\s*t[au],\s*m[au]} 3 } } */ > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,= \s*mf2,\s*t[au],\s*m[au]} 2 } } */ > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,= \s*m1,\s*t[au],\s*m[au]} 2 } } */ > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,= \s*m2,\s*t[au],\s*m[au]} 2 } } */ > /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,= \s*m4,\s*t[au],\s*m[au]} 2 } } */ > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16= ,\s*m8,\s*t[au],\s*m[au]} 1 } } */ > /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]= +} 5 } } */ > /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]= +} 5 } } */ > - > +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\= )} 4 } } */ > -- > 2.34.1 > >