From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf35.google.com (mail-qv1-xf35.google.com [IPv6:2607:f8b0:4864:20::f35]) by sourceware.org (Postfix) with ESMTPS id 0D6313858C54 for ; Wed, 7 Jun 2023 14:13:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0D6313858C54 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qv1-xf35.google.com with SMTP id 6a1803df08f44-6263b2526a0so54263876d6.2 for ; Wed, 07 Jun 2023 07:13:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686147231; x=1688739231; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=5qHMC1OR0lcM9wGIMCmM9U0uPWCN5ltCiVNcZhFlNtM=; b=YSSfJu8CiiBfvraj+k9TXbKs+1TEuoVuvOPdRklsmqleAsaotf579ZVpIVI79dfXJm R1h3+G7wvOxuXlpwW2f6aEaWqWYycYxeN3pkOsbaYOzAS25IIqS9y9925hP+/+oFWkvY Xt0ZIdB4xg+GQgHyezaJm0RyRhIwAOe8/QKVdXS0zrh8sZ48KhJjV11u4J4Otv3bcYQf PTxx9+Fm7pbu39ALExusNLEgwfBlGknySA2m4tWYKVaA7ZElKl6NKu6AcpT/N0I2mrbv CCX/5r9tfwcx55ES9BzP8oZISTCOmASYNjxdXxF0+lGicTwXp5qLMR6gQ6odWJrrOWrA omqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686147231; x=1688739231; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=5qHMC1OR0lcM9wGIMCmM9U0uPWCN5ltCiVNcZhFlNtM=; b=kOotCmnNjJ66fYOW+DHmMI3CUzrZ1Ix3042+cXx5SJZHc8CEbkLXAcqbyhunFhPiBx NVBjvCNTsWWdYBtD2MMenZOlYwuIx49L8NU/gKrv6+1x6L4xj+3eTYQ5KWJBm+PK/fJv 4HmoP6Md42qyrshhlB0bOud/JLt1xg0KIDPUevjywRlQLl6n/A3E4qxbP30L9pzO12ic cUt4tVM9jN0FivLycR8hzybu1F/h0ViON0Mc4iOhdm4n6JJ8SG/lyQk3KvggQ8MYDoer a1yPNWc8xmYd2r8bzO3Q/kKqBhlOSk1jVKm8EDpdvuvMY+qkhpHeg8zC/ILYbGeTavUN SV3A== X-Gm-Message-State: AC+VfDwHtGnmxEKu7pN9o5JtwvB81LTMLpV+rCmr514MViOdPBxoyOB4 TKwCulp9NAUDXxvVoXOeFhLeB4LfGkzSG0GERXTb79Hk X-Google-Smtp-Source: ACHHUZ58htupY6LPK1aVcGENIFIWHDjCVjgFmkxuHxbful1TuCclWMjNjhBzLP4SzXch1+M81XFUr/F0sPFOBCZ3nfQ= X-Received: by 2002:a05:6214:628:b0:625:af4b:4162 with SMTP id a8-20020a056214062800b00625af4b4162mr2974143qvx.14.1686147231078; Wed, 07 Jun 2023 07:13:51 -0700 (PDT) MIME-Version: 1.0 References: <20230607131749.82794-1-rzinsly@ventanamicro.com> In-Reply-To: <20230607131749.82794-1-rzinsly@ventanamicro.com> From: Kito Cheng Date: Wed, 7 Jun 2023 22:13:40 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add Veyron V1 pipeline description To: Raphael Moreira Zinsly Cc: gcc-patches@gcc.gnu.org, jeffreyalaw@gmail.com Content-Type: multipart/alternative; boundary="000000000000bf5cdf05fd8abe25" X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,LIKELY_SPAM_BODY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000bf5cdf05fd8abe25 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable I would like vendor cpu name start with vendor name, like ventana-veyron-v1 which is consistent with all other vendor cpu, and llvm are using same convention too. Raphael Moreira Zinsly =E6=96=BC 2023=E5=B9=B46= =E6=9C=887=E6=97=A5 =E9=80=B1=E4=B8=89=EF=BC=8C21:18=E5=AF=AB=E9=81=93=EF= =BC=9A > gcc/ChangeLog: > > * config/riscv/riscv-cores.def: Add veyron-v1 > core and tune info. > * config/riscv/riscv-opts.h > (riscv_microarchitecture_type): Add veyron-v1. > * config/riscv/riscv.cc (veyron_v1_tune_info): New. > * config/riscv/riscv.md: Include veyron-v1.md. > (tune): Add veyron-v1. > * config/riscv/veyron-v1.md: New file. > * doc/invoke.texi (mcpu): Add veyron-v1. > (mtune): Add veyron-v1. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/divmod-2.c: Enable test for veyron-v1. > --- > gcc/config/riscv/riscv-cores.def | 4 + > gcc/config/riscv/riscv-opts.h | 3 +- > gcc/config/riscv/riscv.cc | 15 +++ > gcc/config/riscv/riscv.md | 3 +- > gcc/config/riscv/veyron-v1.md | 121 ++++++++++++++++++++++ > gcc/doc/invoke.texi | 5 +- > gcc/testsuite/gcc.target/riscv/divmod-2.c | 5 +- > 7 files changed, 149 insertions(+), 7 deletions(-) > create mode 100644 gcc/config/riscv/veyron-v1.md > > diff --git a/gcc/config/riscv/riscv-cores.def > b/gcc/config/riscv/riscv-cores.def > index 7d87ab7ce28..4078439e562 100644 > --- a/gcc/config/riscv/riscv-cores.def > +++ b/gcc/config/riscv/riscv-cores.def > @@ -38,6 +38,7 @@ RISCV_TUNE("sifive-3-series", generic, rocket_tune_info) > RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) > RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) > RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) > +RISCV_TUNE("veyron-v1", veyron_v1, veyron_v1_tune_info) > RISCV_TUNE("size", generic, optimize_size_tune_info) > > #undef RISCV_TUNE > @@ -77,4 +78,7 @@ RISCV_CORE("thead-c906", > "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" > "xtheadcondmov_xtheadfmemidx_xtheadmac_" > "xtheadmemidx_xtheadmempair_xtheadsync", > "thead-c906") > + > +RISCV_CORE("veyron-v1", > "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops", > + "veyron-v1") > #undef RISCV_CORE > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h > index f34ca993689..8f7dd84115f 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -52,7 +52,8 @@ extern enum riscv_isa_spec_class riscv_isa_spec; > /* Keep this list in sync with define_attr "tune" in riscv.md. */ > enum riscv_microarchitecture_type { > generic, > - sifive_7 > + sifive_7, > + veyron_v1 > }; > extern enum riscv_microarchitecture_type riscv_microarchitecture; > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 3954fc07a8b..6a5e89b4813 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -366,6 +366,21 @@ static const struct riscv_tune_param > thead_c906_tune_info =3D { > false /* use_divmod_expansion */ > }; > > +/* Costs to use when optimizing for Ventana Micro Veyron V1. */ > +static const struct riscv_tune_param veyron_v1_tune_info =3D { > + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ > + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ > + {COSTS_N_INSNS (9), COSTS_N_INSNS (17)}, /* fp_div */ > + {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ > + {COSTS_N_INSNS (12), COSTS_N_INSNS (20)}, /* int_div */ > + 4, /* issue_rate */ > + 4, /* branch_cost */ > + 5, /* memory_cost */ > + 8, /* fmv_cost */ > + false, /* slow_unaligned_access = */ > + true, /* use_divmod_expansion */ > +}; > + > /* Costs to use when optimizing for size. */ > static const struct riscv_tune_param optimize_size_tune_info =3D { > {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */ > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 124d8c95804..90f0c1b1cf1 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -482,7 +482,7 @@ > ;; Microarchitectures we know how to tune for. > ;; Keep this in sync with enum riscv_microarchitecture. > (define_attr "tune" > - "generic,sifive_7" > + "generic,sifive_7,veyron_v1" > (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)"))) > > ;; Describe a user's asm statement. > @@ -3123,3 +3123,4 @@ > (include "sifive-7.md") > (include "thead.md") > (include "vector.md") > +(include "veyron-v1.md") > diff --git a/gcc/config/riscv/veyron-v1.md b/gcc/config/riscv/veyron-v1.md > new file mode 100644 > index 00000000000..3eeff76d9b0 > --- /dev/null > +++ b/gcc/config/riscv/veyron-v1.md > @@ -0,0 +1,121 @@ > +;; Scheduling pipeline description for Veyron V1 RISC-V. > +;; Copyright (C) 2023 Free Software Foundation, Inc. > + > +;; This file is part of GCC. > + > +;; GCC is free software; you can redistribute it and/or modify it > +;; under the terms of the GNU General Public License as published > +;; by the Free Software Foundation; either version 3, or (at your > +;; option) any later version. > + > +;; GCC is distributed in the hope that it will be useful, but WITHOUT > +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY > +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public > +;; License for more details. > + > +;; You should have received a copy of the GNU General Public License > +;; along with GCC; see the file COPYING3. If not see > +;; . > + > + > +(define_automaton "veyron_v1") > + > +;; 5 conceptual units of the processor: > +;; The 4 symmetric ALUs > +;; The execution FPU (fadd, fmul, fmadd, comparisons, etc) > +;; The data transfer FPU > +;; The shared multi-cycle ALU for integer mul, div, etc > +;; The fdiv/fsqrt unit in the FPU > + > +(define_cpu_unit "ixu0_v1,ixu1_v1,ixu2_v1,ixu3_v1" "veyron_v1") > +(define_cpu_unit "veyron_v1_fxu" "veyron_v1") > +(define_cpu_unit "veyron_v1_fxu_xfer" "veyron_v1") > + > +(define_cpu_unit "veyron_v1_multi" "veyron_v1") > +(define_cpu_unit "veyron_v1_div" "veyron_v1") > + > +;; Shortcut for reserving one of the symmetric ALU units. > +(define_reservation "veyron_v1_ixu" > + "ixu0_v1|ixu1_v1|ixu2_v1|ixu3_v1") > + > +(define_insn_reservation "veyron_v1_alu" 2 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" > "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,= max,minu,maxu,clz,ctz")) > + "veyron_v1_ixu") > + > +(define_insn_reservation "veyron_v1_store" 1 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "store")) > + "veyron_v1_ixu") > + > +(define_insn_reservation "veyron_v1_ixu" 4 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "load")) > + "veyron_v1_ixu") > + > +(define_insn_reservation "veyron_v1_fpload" 6 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "fpload")) > + "veyron_v1_ixu") > + > +(define_insn_reservation "veyron_v1_xfer" 4 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "mfc,mtc")) > + "veyron_v1_ixu+veyron_v1_multi,veyron_v1_multi*3") > + > +(define_insn_reservation "veyron_v1_fpstore" 1 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "fpstore")) > + "veyron_v1_ixu+veyron_v1_fxu_xfer") > + > +(define_insn_reservation "veyron_v1_fmove" 2 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "fmove")) > + "veyron_v1_ixu+veyron_v1_fxu_xfer") > + > +(define_insn_reservation "veyron_v1_fcvt" 5 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "fcvt")) > + "veyron_v1_ixu+veyron_v1_fxu_xfer") > + > +(define_insn_reservation "veyron_v1_fpcmp" 2 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "fcmp")) > + "veyron_v1_ixu+veyron_v1_fxu") > + > +(define_insn_reservation "veyron_v1_imul" 4 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "imul")) > + "veyron_v1_ixu+veyron_v1_multi") > + > +(define_insn_reservation "veyron_v1_idiv" 20 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "idiv")) > + "veyron_v1_ixu+veyron_v1_multi,veyron_v1_multi*19") > + > +(define_insn_reservation "veyron_v1_fpa" 3 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "fadd,fmul")) > + "veyron_v1_ixu+veyron_v1_fxu") > + > +(define_insn_reservation "veyron_v1_fmadd" 5 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "fmadd")) > + "veyron_v1_ixu+veyron_v1_fxu") > + > +(define_insn_reservation "veyron_v1_fpdivsqrt_single" 9 > + (and (eq_attr "tune" "veyron_v1") > + (and (eq_attr "type" "fdiv,fsqrt") > + (eq_attr "mode" "SF"))) > + "veyron_v1_ixu+veyron_v1_fxu+veyron_v1_div,veyron_v1_div*8") > + > +(define_insn_reservation "veyron_v1_fpdivsqrt_double" 17 > + (and (eq_attr "tune" "veyron_v1") > + (and (eq_attr "type" "fdiv,fsqrt") > + (eq_attr "mode" "DF"))) > + "veyron_v1_ixu+veyron_v1_fxu+veyron_v1_div,veyron_v1_div*16") > + > +(define_insn_reservation "veyron_v1_popcount" 4 > + (and (eq_attr "tune" "veyron_v1") > + (eq_attr "type" "cpop")) > + "veyron_v1_ixu+veyron_v1_multi,veyron_v1_multi*3") > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 898a88ce33e..b163be7ec5e 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -28995,14 +28995,15 @@ by particular CPU name. > Permissible values for this option are: @samp{sifive-e20}, > @samp{sifive-e21}, > @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, > @samp{sifive-e76}, > @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, > @samp{sifive-s76}, > -@samp{sifive-u54}, and @samp{sifive-u74}. > +@samp{sifive-u54}, @samp{sifive-u74} and @samp{veyron-v1}. > > @opindex mtune > @item -mtune=3D@var{processor-string} > Optimize the output for the given processor, specified by > microarchitecture or > particular CPU name. Permissible values for this option are: > @samp{rocket}, > @samp{sifive-3-series}, @samp{sifive-5-series}, @samp{sifive-7-series}, > -@samp{thead-c906}, @samp{size}, and all valid options for @option{-mcpu= =3D}. > +@samp{thead-c906}, @samp{veyron-v1} and @samp{size}, and all valid > options for > +@option{-mcpu=3D}. > > When @option{-mtune=3D} is not specified, use the setting from > @option{-mcpu}, > the default is @samp{rocket} if both are not specified. > diff --git a/gcc/testsuite/gcc.target/riscv/divmod-2.c > b/gcc/testsuite/gcc.target/riscv/divmod-2.c > index dfd319e52c0..67330f88cf8 100644 > --- a/gcc/testsuite/gcc.target/riscv/divmod-2.c > +++ b/gcc/testsuite/gcc.target/riscv/divmod-2.c > @@ -1,7 +1,6 @@ > /* { dg-do compile } */ > -/* Skip this everywhere for now. Once we have a target with > - divmod enabled, only skip for -O0, -O1, -Og, -Oz, -Os. */ > -/* { dg-skip-if "" { *-*-* } { } } */ > +/* { dg-options "-mtune=3Dveyron-v1 -mabi=3Dlp64" } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Oz" "-Os" } } */ > > void > foo(int a, int b, int *c, int *d) > -- > 2.40.1 > > --000000000000bf5cdf05fd8abe25--