From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by sourceware.org (Postfix) with ESMTPS id 30AE33858D1E for ; Mon, 29 Aug 2022 02:14:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 30AE33858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x530.google.com with SMTP id z41so1035337ede.0 for ; Sun, 28 Aug 2022 19:14:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc; bh=fxAitde7jM3O95jWe9qmV/mSYF8s43t0N0LoA0wb+u0=; b=oy7GmdgugcWZLbC7HtsTYHJPa5nlSAnVj8JVOobXSICrxJ6hkKwjhefrNZorc5FS/6 Sp/v8GBq8Xa+sEEcAnpfIxR9Oh4FTm2Vw6eiIiLxDSd+jk4Qn/Z78BYjfopxA8Nbha52 1sB6Wp8vHCOElgQ/2mDA5jwMeoQD6RI9gN6qN55WH8AqPgpS4RYUIBazuJ6ja66UCsJ/ AdiGrs3QCgAKuPqPwDwJILtddErH/sISpzgSn1zr3+FFwuhQabwAdG8Rf2X1ZTCOz3Vz HoFM9uezuTPdfRcAH8XJrP25ssc/AGEy4H/2I1rdw8UF//V1E9q77whAqaC2XjUHyXQg ylGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=fxAitde7jM3O95jWe9qmV/mSYF8s43t0N0LoA0wb+u0=; b=NN5LNtdpb6aHUBLgEutQYTKUhnhA5tEe1UJxHAmCeUqq29JbNyyrYbmUnC0BAdF9xa z7yCJU6JdH8ONKA7jSXWU1Cxa/BDsxXfd5VQXRKjJUUe6oW20g6ALC5yCWeFxo5Tk5ls +K2bfNx6gFmUEW0LcN/PqFYxFO8mkUCdxkDHILzwZBAZIlVUG0pAjhXaGc9CR9ox6kEh sGZ82T+J5YMm6/W/vHbnDIUY9ISFuXaF8jNlWI7MmsjwwNDMERpM/nqFPNGHmG8bgtOn rr0p+M0vmwhUTs7tQqn7A26QJsmPoHJ8GHvVeyjXNzJ0aRrto18cF+b5jemx4If9umvv qaGw== X-Gm-Message-State: ACgBeo37TDAGh32t+9/eu3mz9Pqo8dM+kcSbDJcxPa+llsBwIohCRL7f JHck96ldmLLl8KtTdubfdJ5DlrcagGtIMl2Hdjg= X-Google-Smtp-Source: AA6agR6f6/+nwpTyB9Pn2lhxG3AmqNxtA1YX4IcbGo1NaZOY1SMR8hkcSQHUmbC9jnBzGjRnwBVCisFiBE75G4MOSV4= X-Received: by 2002:aa7:c488:0:b0:448:d11:4830 with SMTP id m8-20020aa7c488000000b004480d114830mr8385304edq.97.1661739277741; Sun, 28 Aug 2022 19:14:37 -0700 (PDT) MIME-Version: 1.0 References: <20220827105723.303520-1-juzhe.zhong@rivai.ai> In-Reply-To: <20220827105723.303520-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Mon, 29 Aug 2022 10:14:25 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add RVV instructions classification To: juzhe.zhong@rivai.ai Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed, thanks! On Sat, Aug 27, 2022 at 6:58 PM wrote: > > From: zhongjuzhe > > gcc/ChangeLog: > > * config/riscv/riscv.md: Add new type for vector instructions. > > --- > gcc/config/riscv/riscv.md | 100 +++++++++++++++++++++++++++++++++++++- > 1 file changed, 99 insertions(+), 1 deletion(-) > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 30cd07dc6f5..ee3e7c53b78 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -195,10 +195,108 @@ > ;; nop no operation > ;; ghost an instruction that produces no real code > ;; bitmanip bit manipulation instructions > +;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. > +;; rdvlenb vector byte length vlenb csrr read > +;; rdvl vector length vl csrr read > +;; 7. Vector Loads and Stores > +;; vlde vector unit-stride load instructions > +;; vste vector unit-stride store instructions > +;; vldm vector unit-stride mask load instructions > +;; vstm vector unit-stride mask store instructions > +;; vlds vector strided load instructions > +;; vsts vector strided store instructions > +;; vldux vector unordered indexed load instructions > +;; vldox vector ordered indexed load instructions > +;; vstux vector unordered indexed store instructions > +;; vstox vector ordered indexed store instructions > +;; vldff vector unit-stride fault-only-first load instructions > +;; vldr vector whole register load instructions > +;; vstr vector whole register store instructions > +;; 11. Vector integer arithmetic instructions > +;; vialu vector single-width integer add and subtract and logical nstructions > +;; viwalu vector widening integer add/subtract > +;; vext vector integer extension > +;; vicalu vector arithmetic with carry or borrow instructions > +;; vshift vector single-width bit shift instructions > +;; vnshift vector narrowing integer shift instructions > +;; vicmp vector integer comparison/min/max instructions > +;; vimul vector single-width integer multiply instructions > +;; vidiv vector single-width integer divide instructions > +;; viwmul vector widening integer multiply instructions > +;; vimuladd vector single-width integer multiply-add instructions > +;; viwmuladd vector widening integer multiply-add instructions > +;; vimerge vector integer merge instructions > +;; vimov vector integer move vector instructions > +;; 12. Vector fixed-point arithmetic instructions > +;; vsalu vector single-width saturating add and subtract and logical instructions > +;; vaalu vector single-width averaging add and subtract and logical instructions > +;; vsmul vector single-width fractional multiply with rounding and saturation instructions > +;; vsshift vector single-width scaling shift instructions > +;; vnclip vector narrowing fixed-point clip instructions > +;; 13. Vector floating-point instructions > +;; vfalu vector single-width floating-point add/subtract instructions > +;; vfwalu vector widening floating-point add/subtract instructions > +;; vfmul vector single-width floating-point multiply instructions > +;; vfdiv vector single-width floating-point divide instructions > +;; vfwmul vector widening floating-point multiply instructions > +;; vfmuladd vector single-width floating-point multiply-add instructions > +;; vfwmuladd vector widening floating-point multiply-add instructions > +;; vfsqrt vector floating-point square-root instructions > +;; vfrecp vector floating-point reciprocal square-root instructions > +;; vfcmp vector floating-point comparison/min/max instructions > +;; vfsgnj vector floating-point sign-injection instructions > +;; vfclass vector floating-point classify instruction > +;; vfmerge vector floating-point merge instruction > +;; vfmov vector floating-point move instruction > +;; vfcvtitof vector single-width integer to floating-point instruction > +;; vfcvtftoi vector single-width floating-point to integer instruction > +;; vfwcvtitof vector widening integer to floating-point instruction > +;; vfwcvtftoi vector widening floating-point to integer instruction > +;; vfwcvtftof vector widening floating-point to floating-point instruction > +;; vfncvtitof vector narrowing integer to floating-point instruction > +;; vfncvtftoi vector narrowing floating-point to integer instruction > +;; vfncvtftof vector narrowing floating-point to floating-point instruction > +;; 14. Vector reduction operations > +;; vired vector single-width integer reduction instructions > +;; viwred vector widening integer reduction instructions > +;; vfred vector single-width floating-point un-ordered reduction instruction > +;; vfredo vector single-width floating-point ordered reduction instruction > +;; vfwred vector widening floating-point un-ordered reduction instruction > +;; vfwredo vector widening floating-point ordered reduction instruction > +;; 15. Vector mask instructions > +;; vmalu vector mask-register logical instructions > +;; vmpop vector mask population count > +;; vmffs vector find-first-set mask bit > +;; vmsfs vector set mask bit > +;; vmiota vector iota > +;; vmidx vector element index instruction > +;; 16. Vector permutation instructions > +;; vimovvx integer scalar move instructions > +;; vimovxv integer scalar move instructions > +;; vfmovvf floating-point scalar move instructions > +;; vfmovfv floating-point scalar move instructions > +;; vislide vector slide instructions > +;; vislide1 vector slide instructions > +;; vfslide1 vector slide instructions > +;; vgather vector register gather instructions > +;; vcompress vector compress instruction > +;; vmov whole vector register move > (define_attr "type" > "unknown,branch,jump,call,load,fpload,store,fpstore, > mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, > - fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate" > + fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, > + rdvlenb,rdvl,vlde,vste,vldm,vstm,vlds,vsts, > + vldux,vldox,vstux,vstox,vldff,vldr,vstr, > + vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp, > + vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov, > + vsalu,vaalu,vsmul,vsshift,vnclip, > + vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp, > + vfcmp,vfsgnj,vfclass,vfmerge,vfmov, > + vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi, > + vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof, > + vired,viwred,vfred,vfredo,vfwred,vfwredo, > + vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, > + vislide,vislide1,vfslide1,vgather,vcompress,vmov" > (cond [(eq_attr "got" "load") (const_string "load") > > ;; If a doubleword move uses these expensive instructions, > -- > 2.24.4 >