From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x22c.google.com (mail-oi1-x22c.google.com [IPv6:2607:f8b0:4864:20::22c]) by sourceware.org (Postfix) with ESMTPS id 811413858D32 for ; Mon, 30 Jan 2023 16:49:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 811413858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oi1-x22c.google.com with SMTP id s124so10583901oif.1 for ; Mon, 30 Jan 2023 08:49:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=4r8vfzGJEXjNwvPN6Dch7fbb5RWTQfnyKg9EAPJait8=; b=mV3FY6iWCSlzscSWywk5B+iD/fY73LlNxdHAdtHkFO+JhOBsUtGhmLSffz2/peXDmd ALLfiHefa9k6il0JKNMOSaKM/AuU5G2C5ihp/OgAZtS4jf0oZALdgIOfk1X1bMmSwz7t 7Z/oObXTEj45Ur/yrSTOqPH6ZwBOiFkLN7BVEzhXU8oVHmVRa9I1r0hb17rVbmP4Sqnn mryqribUlqtWx6ZcVBfbomfcY9bM8oqGjUTBN6Dutg4sJckjNnGLVLH5g/DJ9KhzqbBl YrpmwPqCVS40ibMYCVon6stQn53CwhkcXFnpI45JzpHWfPHv9Bp/rBYgOMvAcnDCOp5K B6UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=4r8vfzGJEXjNwvPN6Dch7fbb5RWTQfnyKg9EAPJait8=; b=hJYWasSHy+QbPIadnC5zZWjio3osdnQJwg3AxA5NlM8ulsT7XEKKGAWj+v3iYvOMr7 MXRnqiV2379GKoyC3u8uEfchuP5CO5fctpntyBOX01I2gTIwYrRF0Utis/SxviyKVgfp PLQSehu6Uz0E5dhZypbGN9WKkUcbhIF/Zb1E7/RhplmT9srmwmfIPYUnHA3PqyteNNDL JjS/8VtW18fCOd8q2x0sBOphJy0fogjDleci/65QPHTfSYk55GLx8H22oTuOFgDFV2Q7 f80E4Ml7HNuJ6N1SeEPbRgvMdBMsTrE4NAqTU4d4hUY4Bwi6RQY9/LoVErrc33UxvC/c Mb6w== X-Gm-Message-State: AO0yUKUwdALOWmVd/pTU2Ea8MQIelbKF9zhkUwjMg5WeB53RPRRP/Guw vViKfoMBe6p2S6oOQ7dt+C/3dVpWPRqrAY7X9gBl14pb8KE= X-Google-Smtp-Source: AK7set+h/FJMf6AH5aSTk8Hr1rDhsfKVgQNlHX1RLCYBQJ6Xs9+zdKIMA6pkSeerIOGUJN72gN/p4oBCFpQlAEmOGKU= X-Received: by 2002:a05:6808:986:b0:378:56e:c8fb with SMTP id a6-20020a056808098600b00378056ec8fbmr412755oic.86.1675097387655; Mon, 30 Jan 2023 08:49:47 -0800 (PST) MIME-Version: 1.0 References: <20230129153457.220337-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230129153457.220337-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Tue, 31 Jan 2023 00:49:24 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add VSETVL testcases for indexed loads/stores. To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: committed, thanks! On Sun, Jan 29, 2023 at 11:35 PM wrote: > > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-76.c: New test. > * gcc.target/riscv/rvv/vsetvl/avl_single-77.c: New test. > > --- > .../riscv/rvv/vsetvl/avl_single-72.c | 27 +++++++++++++++++++ > .../riscv/rvv/vsetvl/avl_single-76.c | 24 +++++++++++++++++ > .../riscv/rvv/vsetvl/avl_single-77.c | 27 +++++++++++++++++++ > 3 files changed, 78 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c > new file mode 100644 > index 00000000000..b1e28abd4fe > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c > @@ -0,0 +1,27 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + size_t vl = 101; > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + > + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl); > + __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl); > + } > + > + for (size_t i = 0; i < n; i++) > + { > + vuint8mf8_t index = __riscv_vle8_v_u8mf8 (in + i + 300, vl); > + vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2 (in + i + 200, index, vl); > + __riscv_vse32_v_f32mf2 (out + i + 200, v2, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c > new file mode 100644 > index 00000000000..1b6e818d209 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c > @@ -0,0 +1,24 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + size_t vl = 101; > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + } > + > + for (size_t i = 0; i < n; i++) > + { > + vuint8mf8_t index = __riscv_vle8_v_u8mf8 (in + i + 300, vl); > + vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + i + 600, vl); > + __riscv_vsoxei8_v_f32mf2 (out + i + 200, index, v, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c > new file mode 100644 > index 00000000000..9fb16052385 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c > @@ -0,0 +1,27 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ > + > +#include "riscv_vector.h" > + > +void f (void * restrict in, void * restrict out, int n, int cond) > +{ > + size_t vl = 101; > + for (size_t i = 0; i < n; i++) > + { > + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); > + __riscv_vse8_v_i8mf8 (out + i, v, vl); > + } > + > + for (size_t i = 0; i < n; i++) > + { > + vbool64_t mask = __riscv_vlm_v_b64 (in + 10000, vl); > + vuint8mf8_t index = __riscv_vle8_v_u8mf8 (in + i + 300, vl); > + vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + i + 30000, vl); > + vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_tumu (mask, v, in + i + 200, index, vl); > + __riscv_vse32_v_f32mf2 (out + i + 200, v2, vl); > + } > +} > + > +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ > + > -- > 2.36.3 >