From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa2a.google.com (mail-vk1-xa2a.google.com [IPv6:2607:f8b0:4864:20::a2a]) by sourceware.org (Postfix) with ESMTPS id 159A03858D33 for ; Fri, 5 May 2023 16:34:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 159A03858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa2a.google.com with SMTP id 71dfb90a1353d-44ff2f8ec9dso1173601e0c.1 for ; Fri, 05 May 2023 09:34:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683304487; x=1685896487; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=8xh0rC0kWAS3POWzetO9gVpaAPvKemmNGk/imm0WhRE=; b=Q+OaZnb4/JU2G/qmeSUOcH3modk7ZIxvbfKuxV8A9e7OFisSfvfWlyusXCs8pay1cm XyPi0/QXHmdLnGFTMnkzyV6xvmsEgH4lu2AV99uIpAynbGvdrjFBI6r6MR9d9n7u2FUT 0rt+AhTC/u6KRuW5qSYk7BwCfD8+va7Ddi14pkkwnUW/Ecf0rhxswC/EH2ScF9SAGZni bgooIHNc1JqJNq54uM+z8/M2HnpdiEGovx+Gm89Mr49OVjJyEcv1m/pr5te/61hNc9NU cH3ezYqQS8oYvFsgzFoeE5uBRzBVn/ydti0vju7oLtk8NREf1euJSZokgd3WCFXbXwZk njUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683304487; x=1685896487; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=8xh0rC0kWAS3POWzetO9gVpaAPvKemmNGk/imm0WhRE=; b=j+apBcEEJH9A+Dni0tG7cz0pGaPmBXpHL3JVTNzVWocv/U67bJiBx54Ewh1YNvLdla 7m/pl4BGj1VZn7GPJG6hV3uRiN5m/u/i0XZnESy99wwSj2Ms936c1QGOUOOTtdg1l1/H h31kenefJvbqvw6KT+fzAfrkEGx+CFmhTSHJK3+VmFz/n+7XzKC1SQU2HGAUbqYB7NgG xmFCO7uHCv2MutkD1WWIsY33Yj5TITNGM1Hxd9Usu8TXkku8MFV1MkB9uo9G6uV6ZK5/ dSh21brnrPHaHQv9gB1IQAXfhPv7iqOI5+b1WoquQKy70DD3dSN4LV1CX09+2c4Iqv2Y Fwag== X-Gm-Message-State: AC+VfDwlYhT2gsDaEvXmZUYraps0gX/nozsl8lRi7zHWj0N5dlGBHrvY agyltQ4uGs1AdXh+M/+ZATasJ8/rGWZeuAeY+CU= X-Google-Smtp-Source: ACHHUZ5tF0DFdXLd77ZCl+Ir0KGbWPsu+GTEHh3fBPG0fz8Qy+Z+ST4EcW66VWwd8SgQccZBlaDNLnyRyOslU3TKoSQ= X-Received: by 2002:a05:6102:a34:b0:42f:fb01:ba37 with SMTP id 20-20020a0561020a3400b0042ffb01ba37mr848621vsb.5.1683304487219; Fri, 05 May 2023 09:34:47 -0700 (PDT) MIME-Version: 1.0 References: <20230505154607.1155567-1-collison@rivosinc.com> In-Reply-To: <20230505154607.1155567-1-collison@rivosinc.com> From: Kito Cheng Date: Sat, 6 May 2023 00:34:36 +0800 Message-ID: Subject: Re: [PATCH v6 0/9] RISC-V: autovec: Add autovec support To: Jeff Law , Michael Collison , Palmer Dabbelt , =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: gcc-patches@gcc.gnu.org Content-Type: multipart/alternative; boundary="00000000000002781605faf4de1e" X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000002781605faf4de1e Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Errr, why you just mixed in JuZhe=E2=80=99s patch set into this patch set? Michael Collison =E6=96=BC 2023=E5=B9=B45=E6=9C=885= =E6=97=A5 =E9=80=B1=E4=BA=94=EF=BC=8C23:47=E5=AF=AB=E9=81=93=EF=BC=9A > This series of patches adds foundational support for RISC-V > auto-vectorization support. These patches are based on the current upstre= am > rvv vector intrinsic support and is not a new implementation. Most of the > implementation consists of adding the new vector cost model, the > autovectorization patterns themselves and target hooks. This implementati= on > only provides support for integer addition and subtraction as a proof of > concept. This patch set should not be construed to be feature complete. > Based on conversations with the community these patches are intended to l= ay > the groundwork for feature completion and collaboration within the RISC-V > community. > > These patches are largely based off the work of Juzhe Zhong ( > juzhe.zhong@rivai.ai) of RiVAI. More > specifically the rvv-next branch at: > https://github.com/riscv-collab/riscv-gcc.git < > https://github.com/riscv-collab/riscv-gcc.git>is the foundation of this > patch set. > > As discussed on this list, if these patches are approved they will be > merged into a "auto-vectorization" branch once gcc-13 branches for releas= e. > There are two known issues related to crashes (assert failures) associated > with tree vectorization; one of which I have sent a patch for and have > received feedback. > > Changes in v6: > - Incorporated upstream comments, added target hook for > TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT > > Changes in v5: > > - Incorporated upstream comments large to delete unnecessary code > > Changes in v4: > > - Added support for binary integer operations and test cases > - Fixed bug to support 8-bit integer vectorization > - Fixed several assert errors related to non-multiple of two vector modes > > Changes in v3: > > - Removed the cost model and cost hooks based on feedback from Richard > Biener > - Used RVV_VUNDEF macro to fix failing patterns > > Changes in v2 > > - Updated ChangeLog entry to include RiVAI contributions > - Fixed ChangeLog email formatting > - Fixed gnu formatting issues in the code > > Kevin Lee (1): > RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv. > > Michael Collison (8): > RISC-V: Add new predicates and function prototypes > RISC-V: autovec: Export policy functions to global scope > RISC-V:autovec: Add auto-vectorization support functions > RISC-V:autovec: Add target vectorization hooks > RISC-V:autovec: Add autovectorization patterns for binary integer & > len_load/store > RISC-V:autovec: Add autovectorization tests for add & sub > vect: Verify that GET_MODE_NUNITS is a multiple of 2. > RISC-V:autovec: Add autovectorization tests for binary integer > > gcc/config/riscv/riscv-opts.h | 10 ++ > gcc/config/riscv/riscv-protos.h | 9 ++ > gcc/config/riscv/riscv-v.cc | 91 ++++++++++++ > gcc/config/riscv/riscv-vector-builtins.cc | 4 +- > gcc/config/riscv/riscv-vector-builtins.h | 3 + > gcc/config/riscv/riscv.cc | 130 ++++++++++++++++++ > gcc/config/riscv/riscv.md | 1 + > gcc/config/riscv/vector-auto.md | 74 ++++++++++ > gcc/config/riscv/vector.md | 4 +- > .../riscv/rvv/autovec/loop-add-rv32.c | 25 ++++ > .../gcc.target/riscv/rvv/autovec/loop-add.c | 25 ++++ > .../riscv/rvv/autovec/loop-and-rv32.c | 25 ++++ > .../gcc.target/riscv/rvv/autovec/loop-and.c | 25 ++++ > .../riscv/rvv/autovec/loop-div-rv32.c | 27 ++++ > .../gcc.target/riscv/rvv/autovec/loop-div.c | 27 ++++ > .../riscv/rvv/autovec/loop-max-rv32.c | 26 ++++ > .../gcc.target/riscv/rvv/autovec/loop-max.c | 26 ++++ > .../riscv/rvv/autovec/loop-min-rv32.c | 26 ++++ > .../gcc.target/riscv/rvv/autovec/loop-min.c | 26 ++++ > .../riscv/rvv/autovec/loop-mod-rv32.c | 27 ++++ > .../gcc.target/riscv/rvv/autovec/loop-mod.c | 27 ++++ > .../riscv/rvv/autovec/loop-mul-rv32.c | 25 ++++ > .../gcc.target/riscv/rvv/autovec/loop-mul.c | 25 ++++ > .../riscv/rvv/autovec/loop-or-rv32.c | 25 ++++ > .../gcc.target/riscv/rvv/autovec/loop-or.c | 25 ++++ > .../riscv/rvv/autovec/loop-sub-rv32.c | 25 ++++ > .../gcc.target/riscv/rvv/autovec/loop-sub.c | 25 ++++ > .../riscv/rvv/autovec/loop-xor-rv32.c | 25 ++++ > .../gcc.target/riscv/rvv/autovec/loop-xor.c | 25 ++++ > gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 + > gcc/tree-vect-slp.cc | 7 +- > 31 files changed, 843 insertions(+), 6 deletions(-) > create mode 100644 gcc/config/riscv/vector-auto.md > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c > > -- > 2.34.1 > > --00000000000002781605faf4de1e--