From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa32.google.com (mail-vk1-xa32.google.com [IPv6:2607:f8b0:4864:20::a32]) by sourceware.org (Postfix) with ESMTPS id DC4FB3858C60 for ; Mon, 18 Sep 2023 03:36:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC4FB3858C60 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa32.google.com with SMTP id 71dfb90a1353d-490cd6db592so1715102e0c.1 for ; Sun, 17 Sep 2023 20:36:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695008193; x=1695612993; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=FZKylKidPvU9uV3640sn1MO9LlOcOVhAPtRYe85VYZ4=; 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DAVo1DlAeqRGbXsifHDzWX+u4VnQKQQYIAhw5OcLYGt0VawG8dDvd5JEqoneh/rRU2lm fnzQ== X-Gm-Message-State: AOJu0YxkYTy3JbQN9SYyOQFeNrAKl0Ifet6rZ5e0mNhHTFRz0dUxTAFX g/SArLBWb/7tJBrF3y6l/2TKB4OpkiqphDVbf/Q= X-Google-Smtp-Source: AGHT+IGQdEhVs/Gu3ZjT4Sdin/Q35//JpPzyLk1P0ZVeAp36Caw0y/44OPANjm1H9Em60qRLS7ZjywS0lxosFOoPM1A= X-Received: by 2002:a1f:eac3:0:b0:490:411c:e593 with SMTP id i186-20020a1feac3000000b00490411ce593mr5038148vkh.15.1695008193153; Sun, 17 Sep 2023 20:36:33 -0700 (PDT) MIME-Version: 1.0 References: <20230918032711.3807244-1-pan2.li@intel.com> In-Reply-To: <20230918032711.3807244-1-pan2.li@intel.com> From: Kito Cheng Date: Mon, 18 Sep 2023 11:36:21 +0800 Message-ID: Subject: Re: [PATCH v1] RISC-V: Support VLS mode for vec_set To: pan2.li@intel.com Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, yanzhang.wang@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM On Mon, Sep 18, 2023 at 11:27=E2=80=AFAM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch would like to add the VLS support vec_set, both INT > and FP are included. > > Give sample code as below: > > typedef long long vl_t \ > __attribute__((vector_size(2 * sizeof (long long)))); > > vl_t init_vl (vl_t v, unsigned index, unsigned value) > { > v[index] =3D value; > > return v; > } > > Before this patch: > init_vl: > addi sp,sp,-16 > vsetivli zero,2,e64,m1,ta,ma > vle64.v v1,0(a1) > vse64.v v1,0(sp) > slli a4,a2,32 > srli a2,a4,29 > add a2,sp,a2 > slli a3,a3,32 > srli a3,a3,32 > sd a3,0(a2) > vle64.v v1,0(sp) > vse64.v v1,0(a0) > addi sp,sp,16 > jr ra > > After this patch: > init_vl: > vsetivli zero,2,e64,m1,ta,ma > vle64.v v1,0(a1) > slli a3,a3,32 > srli a3,a3,32 > addi a5,a2,1 > vsetvli zero,a5,e64,m1,tu,ma > vmv.v.x v2,a3 > vslideup.vx v1,v2,a2 > vsetivli zero,2,e64,m1,ta,ma > vse64.v v1,0(a0) > ret > > Please note this patch depends the RVV SCALAR_MOVE_MERGED_OP bugfix. > > gcc/ChangeLog: > > * config/riscv/autovec.md: Extend to vls mode. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/vls/def.h: New macros. > * gcc.target/riscv/rvv/autovec/vls/vec-set-1.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-10.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-11.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-12.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-13.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-14.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-15.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-16.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-17.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-18.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-19.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-2.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-20.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-21.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-22.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-3.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-4.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-5.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-6.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-7.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-8.c: New test. > * gcc.target/riscv/rvv/autovec/vls/vec-set-9.c: New test. > > Signed-off-by: Pan Li > --- > gcc/config/riscv/autovec.md | 4 +-- > .../gcc.target/riscv/rvv/autovec/vls/def.h | 18 ++++++++++ > .../riscv/rvv/autovec/vls/vec-set-1.c | 35 +++++++++++++++++++ > .../riscv/rvv/autovec/vls/vec-set-10.c | 31 ++++++++++++++++ > .../riscv/rvv/autovec/vls/vec-set-11.c | 29 +++++++++++++++ > .../riscv/rvv/autovec/vls/vec-set-12.c | 21 +++++++++++ > .../riscv/rvv/autovec/vls/vec-set-13.c | 20 +++++++++++ > .../riscv/rvv/autovec/vls/vec-set-14.c | 19 ++++++++++ > .../riscv/rvv/autovec/vls/vec-set-15.c | 18 ++++++++++ > .../riscv/rvv/autovec/vls/vec-set-16.c | 21 +++++++++++ > .../riscv/rvv/autovec/vls/vec-set-17.c | 20 +++++++++++ > .../riscv/rvv/autovec/vls/vec-set-18.c | 19 ++++++++++ > .../riscv/rvv/autovec/vls/vec-set-19.c | 18 ++++++++++ > .../riscv/rvv/autovec/vls/vec-set-2.c | 33 +++++++++++++++++ > .../riscv/rvv/autovec/vls/vec-set-20.c | 20 +++++++++++ > .../riscv/rvv/autovec/vls/vec-set-21.c | 19 ++++++++++ > .../riscv/rvv/autovec/vls/vec-set-22.c | 18 ++++++++++ > .../riscv/rvv/autovec/vls/vec-set-3.c | 31 ++++++++++++++++ > .../riscv/rvv/autovec/vls/vec-set-4.c | 29 +++++++++++++++ > .../riscv/rvv/autovec/vls/vec-set-5.c | 35 +++++++++++++++++++ > .../riscv/rvv/autovec/vls/vec-set-6.c | 33 +++++++++++++++++ > .../riscv/rvv/autovec/vls/vec-set-7.c | 31 ++++++++++++++++ > .../riscv/rvv/autovec/vls/vec-set-8.c | 29 +++++++++++++++ > .../riscv/rvv/autovec/vls/vec-set-9.c | 33 +++++++++++++++++ > 24 files changed, 582 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-10.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-11.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-12.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-13.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-14.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-15.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-16.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-17.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-18.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-19.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-20.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-21.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-22.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-5.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-6.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-7.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-8.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-se= t-9.c > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index 01291ad9830..ac680114b5e 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -1393,9 +1393,9 @@ (define_expand "select_vl" > ;; ---------------------------------------------------------------------= ---- > > (define_expand "vec_set" > - [(match_operand:V 0 "register_operand") > + [(match_operand:V_VLS 0 "register_operand") > (match_operand: 1 "register_operand") > - (match_operand 2 "nonmemory_operand")] > + (match_operand 2 "nonmemory_operand")] > "TARGET_VECTOR" > { > /* If we set the first element, emit an v(f)mv.s.[xf]. */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/t= estsuite/gcc.target/riscv/rvv/autovec/vls/def.h > index 81c4570836b..446eee498de 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > @@ -266,3 +266,21 @@ typedef double v512df __attribute__ ((vector_size (4= 096))); > for (int i =3D 0; i < NUM; ++i) = \ > a[i] =3D b[i] * CALL (1.0, c[i]); = \ > } > + > +#define DEF_VEC_SET_IMM_INDEX(PREFIX, VECTOR, TYPE, INDEX) = \ > + VECTOR __attribute__ ((noinline, noclone)) = \ > + PREFIX##_##VECTOR##_##INDEX (VECTOR v, TYPE a) = \ > + { = \ > + v[INDEX] =3D a; = \ > + = \ > + return v; = \ > + } > + > +#define DEF_VEC_SET_SCALAR_INDEX(PREFIX, VECTOR, TYPE) = \ > + VECTOR __attribute__ ((noinline, noclone)) = \ > + PREFIX##_##VECTOR##_##TYPE (VECTOR v, TYPE a, unsigned index) = \ > + { = \ > + v[index] =3D a; = \ > + = \ > + return v; = \ > + } > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c b= /gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c > new file mode 100644 > index 00000000000..d53fdc22162 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c > @@ -0,0 +1,35 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v1qi, int8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2qi, int8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4qi, int8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8qi, int8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16qi, int8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32qi, int8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64qi, int8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128qi, int8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256qi, int8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512qi, int8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024qi, int8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2048qi, int8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4096qi, int8_t, 0) > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v2qi, int8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4qi, int8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8qi, int8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16qi, int8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32qi, int8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64qi, int8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128qi, int8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256qi, int8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512qi, int8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024qi, int8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2048qi, int8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4096qi, int8_t, 1) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+= } 12 } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,= \s*1} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c > new file mode 100644 > index 00000000000..c9242362372 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c > @@ -0,0 +1,31 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v1sf, float, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2sf, float, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4sf, float, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8sf, float, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16sf, float, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32sf, float, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64sf, float, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128sf, float, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256sf, float, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512sf, float, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024sf, float, 0) > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v2sf, float, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4sf, float, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8sf, float, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16sf, float, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32sf, float, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64sf, float, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128sf, float, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256sf, float, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512sf, float, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024sf, float, 1) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vfmv\.s\.f\s+v[0-9]+,\s*[fa]+[0-9]= +} 10 } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,= \s*1} 10 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c > new file mode 100644 > index 00000000000..4ec86789d80 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c > @@ -0,0 +1,29 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v1df, double, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2df, double, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4df, double, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8df, double, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16df, double, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32df, double, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64df, double, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128df, double, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256df, double, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512df, double, 0) > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v2df, double, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4df, double, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8df, double, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16df, double, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32df, double, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64df, double, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128df, double, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256df, double, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512df, double, 1) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vfmv\.s\.f\s+v[0-9]+,\s*[fa]+[0-9]= +} 9 } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,= \s*1} 9 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c > new file mode 100644 > index 00000000000..4436830307b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c > @@ -0,0 +1,21 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1qi, int8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2qi, int8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4qi, int8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8qi, int8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16qi, int8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32qi, int8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64qi, int8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128qi, int8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256qi, int8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512qi, int8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024qi, int8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048qi, int8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4096qi, int8_t) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,= \s*[axt][0-9]+} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c > new file mode 100644 > index 00000000000..037a4a6f71a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1hi, int16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2hi, int16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4hi, int16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8hi, int16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16hi, int16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32hi, int16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64hi, int16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128hi, int16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256hi, int16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512hi, int16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024hi, int16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048hi, int16_t) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,= \s*[axt][0-9]+} 11 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c > new file mode 100644 > index 00000000000..4dd58884d79 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1si, int32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2si, int32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4si, int32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8si, int32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16si, int32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32si, int32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64si, int32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128si, int32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256si, int32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512si, int32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024si, int32_t) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,= \s*[atx][0-9]+} 10 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c > new file mode 100644 > index 00000000000..77eeed49a99 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1di, int64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2di, int64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4di, int64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8di, int64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16di, int64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32di, int64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64di, int64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128di, int64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256di, int64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512di, int64_t) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,= \s*[atx][0-9]+} 9 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c > new file mode 100644 > index 00000000000..4f2bb2c7508 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c > @@ -0,0 +1,21 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1uqi, uint8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2uqi, uint8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4uqi, uint8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8uqi, uint8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16uqi, uint8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32uqi, uint8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64uqi, uint8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128uqi, uint8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256uqi, uint8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512uqi, uint8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024uqi, uint8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048uqi, uint8_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4096uqi, uint8_t) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,= \s*[atx][0-9]+} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c > new file mode 100644 > index 00000000000..9376aee2ac2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1uhi, uint16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2uhi, uint16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4uhi, uint16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8uhi, uint16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16uhi, uint16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32uhi, uint16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64uhi, uint16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128uhi, uint16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256uhi, uint16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512uhi, uint16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024uhi, uint16_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048uhi, uint16_t) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,= \s*[atx][0-9]+} 11 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c > new file mode 100644 > index 00000000000..ade887ea3be > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1usi, uint32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2usi, uint32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4usi, uint32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8usi, uint32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16usi, uint32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32usi, uint32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64usi, uint32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128usi, uint32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256usi, uint32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512usi, uint32_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024usi, uint32_t) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,= \s*[atx][0-9]+} 10 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c > new file mode 100644 > index 00000000000..7106bd936ad > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1udi, uint64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2udi, uint64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4udi, uint64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8udi, uint64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16udi, uint64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32udi, uint64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64udi, uint64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128udi, uint64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256udi, uint64_t) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512udi, uint64_t) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,= \s*[atx][0-9]+} 9 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c b= /gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c > new file mode 100644 > index 00000000000..6132bb4945a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c > @@ -0,0 +1,33 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v1hi, int16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2hi, int16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4hi, int16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8hi, int16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16hi, int16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32hi, int16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64hi, int16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128hi, int16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256hi, int16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512hi, int16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024hi, int16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2048hi, int16_t, 0) > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v2hi, int16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4hi, int16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8hi, int16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16hi, int16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32hi, int16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64hi, int16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128hi, int16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256hi, int16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512hi, int16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024hi, int16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2048hi, int16_t, 1) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+= } 11 } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,= \s*1} 11 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c > new file mode 100644 > index 00000000000..2da3e3c18a4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1hf, _Float16) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2hf, _Float16) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4hf, _Float16) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8hf, _Float16) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16hf, _Float16) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32hf, _Float16) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64hf, _Float16) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128hf, _Float16) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256hf, _Float16) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512hf, _Float16) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024hf, _Float16) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2048hf, _Float16) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,= \s*[atx][0-9]+} 11 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c > new file mode 100644 > index 00000000000..db2682ad3fd > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1sf, float) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2sf, float) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4sf, float) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8sf, float) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16sf, float) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32sf, float) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64sf, float) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128sf, float) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256sf, float) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512sf, float) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1024sf, float) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,= \s*[atx][0-9]+} 10 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c > new file mode 100644 > index 00000000000..3bb3936c006 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v1df, double) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v2df, double) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v4df, double) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v8df, double) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v16df, double) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v32df, double) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v64df, double) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v128df, double) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v256df, double) > +DEF_VEC_SET_SCALAR_INDEX (vec_set, v512df, double) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vx\s+v[0-9]+,\s*v[0-9]+,= \s*[axt][0-9]+} 9 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c b= /gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c > new file mode 100644 > index 00000000000..6080060b60d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c > @@ -0,0 +1,31 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v1si, int32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2si, int32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4si, int32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8si, int32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16si, int32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32si, int32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64si, int32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128si, int32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256si, int32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512si, int32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024si, int32_t, 0) > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v2si, int32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4si, int32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8si, int32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16si, int32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32si, int32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64si, int32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128si, int32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256si, int32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512si, int32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024si, int32_t, 1) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+= } 10 } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,= \s*1} 10 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c b= /gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c > new file mode 100644 > index 00000000000..09852f7ca1d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c > @@ -0,0 +1,29 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v1di, int64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2di, int64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4di, int64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8di, int64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16di, int64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32di, int64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64di, int64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128di, int64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256di, int64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512di, int64_t, 0) > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v2di, int64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4di, int64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8di, int64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16di, int64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32di, int64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64di, int64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128di, int64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256di, int64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512di, int64_t, 1) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+= } 9 } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,= \s*1} 9 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c b= /gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c > new file mode 100644 > index 00000000000..b6a4d1a2c8b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c > @@ -0,0 +1,35 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v1uqi, uint8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2uqi, uint8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4uqi, uint8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8uqi, uint8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16uqi, uint8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32uqi, uint8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64uqi, uint8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128uqi, uint8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256uqi, uint8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512uqi, uint8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024uqi, uint8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2048uqi, uint8_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4096uqi, uint8_t, 0) > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v2uqi, uint8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4uqi, uint8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8uqi, uint8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16uqi, uint8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32uqi, uint8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64uqi, uint8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128uqi, uint8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256uqi, uint8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512uqi, uint8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024uqi, uint8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2048uqi, uint8_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4096uqi, uint8_t, 1) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+= } 12 } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,= \s*1} 12 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c b= /gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c > new file mode 100644 > index 00000000000..11e22db53f4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c > @@ -0,0 +1,33 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v1uhi, uint16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2uhi, uint16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4uhi, uint16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8uhi, uint16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16uhi, uint16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32uhi, uint16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64uhi, uint16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128uhi, uint16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256uhi, uint16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512uhi, uint16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024uhi, uint16_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2048uhi, uint16_t, 0) > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v2uhi, uint16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4uhi, uint16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8uhi, uint16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16uhi, uint16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32uhi, uint16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64uhi, uint16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128uhi, uint16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256uhi, uint16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512uhi, uint16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024uhi, uint16_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2048uhi, uint16_t, 1) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+= } 11 } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,= \s*1} 11 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c b= /gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c > new file mode 100644 > index 00000000000..d4ce093f201 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c > @@ -0,0 +1,31 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v1usi, uint32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2usi, uint32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4usi, uint32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8usi, uint32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16usi, uint32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32usi, uint32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64usi, uint32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128usi, uint32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256usi, uint32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512usi, uint32_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024usi, uint32_t, 0) > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v2usi, uint32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4usi, uint32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8usi, uint32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16usi, uint32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32usi, uint32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64usi, uint32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128usi, uint32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256usi, uint32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512usi, uint32_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024usi, uint32_t, 1) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+= } 10 } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,= \s*1} 10 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c b= /gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c > new file mode 100644 > index 00000000000..4beb2b0b9be > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c > @@ -0,0 +1,29 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v1udi, uint64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2udi, uint64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4udi, uint64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8udi, uint64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16udi, uint64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32udi, uint64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64udi, uint64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128udi, uint64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256udi, uint64_t, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512udi, uint64_t, 0) > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v2udi, uint64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4udi, uint64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8udi, uint64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16udi, uint64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32udi, uint64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64udi, uint64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128udi, uint64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256udi, uint64_t, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512udi, uint64_t, 1) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vmv\.s\.x\s+v[0-9]+,\s*[atx][0-9]+= } 9 } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,= \s*1} 9 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c b= /gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c > new file mode 100644 > index 00000000000..b59f3f3d121 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c > @@ -0,0 +1,33 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv_zvfh_zvl4096b -mabi=3Dlp64d -O3 -fno-s= chedule-insns -fno-schedule-insns2 --param=3Driscv-autovec-lmul=3Dm8" } */ > + > +#include "def.h" > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v1hf, _Float16, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2hf, _Float16, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4hf, _Float16, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8hf, _Float16, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16hf, _Float16, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32hf, _Float16, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64hf, _Float16, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128hf, _Float16, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256hf, _Float16, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512hf, _Float16, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024hf, _Float16, 0) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2048hf, _Float16, 0) > + > +DEF_VEC_SET_IMM_INDEX (vec_set, v2hf, _Float16, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v4hf, _Float16, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v8hf, _Float16, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v16hf, _Float16, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v32hf, _Float16, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v64hf, _Float16, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v128hf, _Float16, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v256hf, _Float16, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v512hf, _Float16, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v1024hf, _Float16, 1) > +DEF_VEC_SET_IMM_INDEX (vec_set, v2048hf, _Float16, 1) > + > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-assembler-times {vfmv\.s\.f\s+v[0-9]+,\s*[fa]+[0-9]= +} 11 } } */ > +/* { dg-final { scan-assembler-times {vslideup\.vi\s+v[0-9]+,\s*v[0-9]+,= \s*1} 11 } } */ > -- > 2.34.1 >