From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by sourceware.org (Postfix) with ESMTPS id 3D7973858D20 for ; Tue, 1 Mar 2022 14:00:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3D7973858D20 Received: by mail-ej1-x630.google.com with SMTP id a8so31674616ejc.8 for ; Tue, 01 Mar 2022 06:00:00 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=EiFsGjtVXMIkEClRJyez1jcDE19+mkWrT/eSXx8SwJg=; b=US5t1a0OYIvPhNKSX4TSJEQwoaXqAB0Kic2OatkFApLmaMOPgI7xBzUdiUUWO35ea8 fhRfOfUfmzwv611dj2FppYx5hhJ1TcfD+FIDBXsXqpK3rFK9B0nYtv6+Tl6CJOhrrC2b pwzhiJHUByDkE81qe65Y5Fs9kPE/lF7wd4S3g1imW3tIk+ZH6pjfSuHHy9kM4q7StyDi 38DdTqCh0+PJIV8/GyYoRDte9XsJkAo58lIWBPYvQviMp8V+c2jzDZ0IQM78nqdg+wa5 PJOdHZxIozjZyY6Ts33st4/4xcIpYblLaAoiaKitVXF0TfedzCBvmuX56PDu8kxXoc8A 0IFA== X-Gm-Message-State: AOAM5331lhfe0k6o5WZFRz2GbFElYVVTZVnLmdnq3RV7nqJAb7cEeFCh BXvVXulOUy74TPH236IPvWN84Np8yvyPVso24Vo= X-Google-Smtp-Source: ABdhPJy77pa7tJ6HK0pk+tH/7wFinAfIE0HD5tqBXfqmCqe2H/+QiC4RuAkuvjru031sTN/4gd7VLhHjF0uAGxafxAw= X-Received: by 2002:a17:906:f85:b0:6d6:e97b:d276 with SMTP id q5-20020a1709060f8500b006d6e97bd276mr1619035ejj.431.1646143198978; Tue, 01 Mar 2022 05:59:58 -0800 (PST) MIME-Version: 1.0 References: <20220214022554.1590-1-shihua@iscas.ac.cn> In-Reply-To: <20220214022554.1590-1-shihua@iscas.ac.cn> From: Kito Cheng Date: Tue, 1 Mar 2022 21:59:47 +0800 Message-ID: Subject: Re: [PATCH] RISC-V:Add support for ZMMUL extension To: =?UTF-8?B?5buW5LuV5Y2O?= Cc: GCC Patches , Philipp Tomsich , jiawei Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Mar 2022 14:00:02 -0000 LGTM for GCC 13, I'll commit that once stage 1 is open again. On Mon, Feb 14, 2022 at 10:26 AM wrote: > > From: LiaoShihua > > ZMMUL extension is Multiply only extension for RISC-V.It implements the multiplication subset of the M extension. > The encodings are identical to those of the corresponding M-extension instructions. > When You both use M extension add ZMMUL extension, it will warning "-mdiv cannot use when the ZMMUL extension is present" > > gcc\ChangeLog: > > * common/config/riscv/riscv-common.cc:Add support for ZMMUL extension > * config/riscv/riscv-opts.h (MASK_ZMMUL):Likewise > (TARGET_ZMMUL):Likewise > * config/riscv/riscv.cc (riscv_option_override):Likewise > * config/riscv/riscv.md:Likewise > * config/riscv/riscv.opt:Likewise > --- > gcc/common/config/riscv/riscv-common.cc | 3 +++ > gcc/config/riscv/riscv-opts.h | 3 +++ > gcc/config/riscv/riscv.cc | 4 +++- > gcc/config/riscv/riscv.md | 28 ++++++++++++------------- > gcc/config/riscv/riscv.opt | 3 +++ > 5 files changed, 26 insertions(+), 15 deletions(-) > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc > index a904893b9ed..fec6c25eb04 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -185,6 +185,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = > {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, > {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, > > + {"zmmul", ISA_SPEC_CLASS_NONE, 0, 1}, > + > /* Terminate the list. */ > {NULL, ISA_SPEC_CLASS_NONE, 0, 0} > }; > @@ -1080,6 +1082,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = > {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, > {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, > > + {"zmmul", &gcc_options::x_riscv_zmmul_subext, MASK_ZMMUL}, > > {NULL, NULL, 0} > }; > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h > index 929e4e3a7c5..47e25628635 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -136,4 +136,7 @@ enum stack_protector_guard { > #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) > #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) > > +#define MASK_ZMMUL (1 << 0) > +#define TARGET_ZMMUL ((riscv_zmmul_subext & MASK_ZMMUL) != 0) > + > #endif /* ! GCC_RISCV_OPTS_H */ > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 6885b4bbad2..bbd5c288da9 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -4974,8 +4974,10 @@ riscv_option_override (void) > > /* The presence of the M extension implies that division instructions > are present, so include them unless explicitly disabled. */ > - if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0) > + if (!TARGET_ZMMUL && TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0) > target_flags |= MASK_DIV; > + else if(TARGET_ZMMUL && TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0) > + warning (0, "%<-mdiv%> cannot use when the % extension is present"); > else if (!TARGET_MUL && TARGET_DIV) > error ("%<-mdiv%> requires %<-march%> to subsume the % extension"); > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index b3c5bce842a..6dee2fb681a 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -756,7 +756,7 @@ > [(set (match_operand:SI 0 "register_operand" "=r") > (mult:SI (match_operand:SI 1 "register_operand" " r") > (match_operand:SI 2 "register_operand" " r")))] > - "TARGET_MUL" > + "TARGET_ZMMUL || TARGET_MUL" > { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; } > [(set_attr "type" "imul") > (set_attr "mode" "SI")]) > @@ -765,7 +765,7 @@ > [(set (match_operand:DI 0 "register_operand" "=r") > (mult:DI (match_operand:DI 1 "register_operand" " r") > (match_operand:DI 2 "register_operand" " r")))] > - "TARGET_MUL && TARGET_64BIT" > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" > "mul\t%0,%1,%2" > [(set_attr "type" "imul") > (set_attr "mode" "DI")]) > @@ -775,7 +775,7 @@ > (mult:GPR (match_operand:GPR 1 "register_operand" " r") > (match_operand:GPR 2 "register_operand" " r"))) > (label_ref (match_operand 3 "" ""))] > - "TARGET_MUL" > + "TARGET_ZMMUL || TARGET_MUL" > { > if (TARGET_64BIT && mode == SImode) > { > @@ -820,7 +820,7 @@ > (mult:GPR (match_operand:GPR 1 "register_operand" " r") > (match_operand:GPR 2 "register_operand" " r"))) > (label_ref (match_operand 3 "" ""))] > - "TARGET_MUL" > + "TARGET_ZMMUL || TARGET_MUL" > { > if (TARGET_64BIT && mode == SImode) > { > @@ -866,7 +866,7 @@ > (sign_extend:DI > (mult:SI (match_operand:SI 1 "register_operand" " r") > (match_operand:SI 2 "register_operand" " r"))))] > - "TARGET_MUL && TARGET_64BIT" > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" > "mulw\t%0,%1,%2" > [(set_attr "type" "imul") > (set_attr "mode" "SI")]) > @@ -877,7 +877,7 @@ > (match_operator:SI 3 "subreg_lowpart_operator" > [(mult:DI (match_operand:DI 1 "register_operand" " r") > (match_operand:DI 2 "register_operand" " r"))])))] > - "TARGET_MUL && TARGET_64BIT" > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" > "mulw\t%0,%1,%2" > [(set_attr "type" "imul") > (set_attr "mode" "SI")]) > @@ -895,7 +895,7 @@ > [(set (match_operand:TI 0 "register_operand") > (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) > (any_extend:TI (match_operand:DI 2 "register_operand"))))] > - "TARGET_MUL && TARGET_64BIT" > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" > { > rtx low = gen_reg_rtx (DImode); > emit_insn (gen_muldi3 (low, operands[1], operands[2])); > @@ -917,7 +917,7 @@ > (any_extend:TI > (match_operand:DI 2 "register_operand" " r"))) > (const_int 64))))] > - "TARGET_MUL && TARGET_64BIT" > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" > "mulh\t%0,%1,%2" > [(set_attr "type" "imul") > (set_attr "mode" "DI")]) > @@ -926,7 +926,7 @@ > [(set (match_operand:TI 0 "register_operand") > (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand")) > (sign_extend:TI (match_operand:DI 2 "register_operand"))))] > - "TARGET_MUL && TARGET_64BIT" > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" > { > rtx low = gen_reg_rtx (DImode); > emit_insn (gen_muldi3 (low, operands[1], operands[2])); > @@ -948,7 +948,7 @@ > (sign_extend:TI > (match_operand:DI 2 "register_operand" " r"))) > (const_int 64))))] > - "TARGET_MUL && TARGET_64BIT" > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" > "mulhsu\t%0,%2,%1" > [(set_attr "type" "imul") > (set_attr "mode" "DI")]) > @@ -959,7 +959,7 @@ > (match_operand:SI 1 "register_operand" " r")) > (any_extend:DI > (match_operand:SI 2 "register_operand" " r"))))] > - "TARGET_MUL && !TARGET_64BIT" > + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" > { > rtx temp = gen_reg_rtx (SImode); > emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); > @@ -978,7 +978,7 @@ > (any_extend:DI > (match_operand:SI 2 "register_operand" " r"))) > (const_int 32))))] > - "TARGET_MUL && !TARGET_64BIT" > + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" > "mulh\t%0,%1,%2" > [(set_attr "type" "imul") > (set_attr "mode" "SI")]) > @@ -990,7 +990,7 @@ > (match_operand:SI 1 "register_operand" " r")) > (sign_extend:DI > (match_operand:SI 2 "register_operand" " r"))))] > - "TARGET_MUL && !TARGET_64BIT" > + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" > { > rtx temp = gen_reg_rtx (SImode); > emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); > @@ -1009,7 +1009,7 @@ > (sign_extend:DI > (match_operand:SI 2 "register_operand" " r"))) > (const_int 32))))] > - "TARGET_MUL && !TARGET_64BIT" > + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" > "mulhsu\t%0,%2,%1" > [(set_attr "type" "imul") > (set_attr "mode" "SI")]) > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index 9fffc08220d..46f695b97d3 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -209,6 +209,9 @@ int riscv_vector_eew_flags > TargetVariable > int riscv_zvl_flags > > +TargetVariable > +int riscv_zmmul_subext > + > Enum > Name(isa_spec_class) Type(enum riscv_isa_spec_class) > Supported ISA specs (for use with the -misa-spec= option): > -- > 2.31.1.windows.1 >