From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa2c.google.com (mail-vk1-xa2c.google.com [IPv6:2607:f8b0:4864:20::a2c]) by sourceware.org (Postfix) with ESMTPS id BDCEB3858404 for ; Fri, 27 Oct 2023 07:48:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BDCEB3858404 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BDCEB3858404 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::a2c ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698392896; cv=none; b=Dk1pYqos6V4iHfsemVNoP6pry+aHEiQH1xcb8XP3tPpkvZ6W5XjpvJML4oprTGfVuXUSvj0U0n3qd7Uzod4yDt8Layjcl8gh1ZaHsyjZQrCMsMI+G3AUC/zg4deDhooF8RgnIWsXf/Eyf/eHQOnqZQ5YTa/9vVnVlnIwqlH8qB0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698392896; c=relaxed/simple; bh=CMcoEP1kSi6IBXvOmVt+zv75ZNA21CBBObMLD6N4ZDo=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=SdIVdewF84OnwH5nmbYKCtugHP+oxb/amjItTs7K4tdF/zW92j/8jXa7WuNaIp0D8Cqs9aBCzQiF1KImFZbsnJOocqvGz/har3cAgQccnxjsLfRK2ltAGHDYGTn+JCUtw4jzoKA5HK6GvfpokeKNwbUUfEPDkj/FBX7AKC20P5Y= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-vk1-xa2c.google.com with SMTP id 71dfb90a1353d-49dd3bb5348so797264e0c.0 for ; Fri, 27 Oct 2023 00:48:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1698392885; x=1698997685; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=zKM+iduWi1QxriJEWDvFpkWFC4nVPLNbL7bIIWCQX94=; b=UL2j6FO3gqzloTbuWWqTddzAfD4XE0ElGhXT/IrFB6iNskWy5vofUpXXC0X5nWh/IF mMJCCjiW/QwDWR/Nu7vHNIoo55tQdxTwZSYOmKiHMV8EAJlQRdtoHxlszb1WkkOjcTqa 4r1ygLF2zNaflCoO3K1VvyQaOibumko7hqovF76KvAkU1V+h9Xv2Z7ZdTax7JsDVwnLd 22z6PpFS5oQYFsqWHWScfJGKh0IsxR55T1gt4zpK+PmUdnLPIaW71TPdm7ZR4Nfy1a30 3sW5UiVpUHg0Wb9RliSEqvdwXAWpErA7wWOJbGp01P3wh9JsSWEhdmqb9rnazSSFpBGt fQdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698392885; x=1698997685; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zKM+iduWi1QxriJEWDvFpkWFC4nVPLNbL7bIIWCQX94=; b=mdfJgeFJYyeZIFJRG3pmu+4YR3sooOKEeltG3SGY/kmYJy31XtLDDZqVAPFV3rUnjo mVlPEpeBcgQ8CgxMZrPPv1l7VVxPL5zZZWOUlqSL4UjDGozr5mfv+KHVdyy3YVYtSRdO fBU1G/dxUHscFeC8igD7G73PkytT1FoIVCAo/9ExRYY10YiNNsjGj5oo2Bt/Uqwn/VJx BcujCf7DcwkbXPkndszV1s2C+HdowrjABcuwhb0pd+hnZYTTQp+JyTtiSEeFomrOveKs MpHeS//qA/lyW1tStrPGwniMH+e7qIUKBG0s4duKxuKO46EYahmbd7T2yHqUOFTbANF+ ISsw== X-Gm-Message-State: AOJu0YxD2wu2P6EAFJjYm3z5lmyzOmzftnD0WmnClN/Sko1GrcTI+9ic hwi2T4CLZagO+chwX2pc3RP0Z7NI5MJ4TawWvKY= X-Google-Smtp-Source: AGHT+IEjmSwkSEOrqcrxqpPglGAewN+NyFITWcWX2dxDOzd9Iv5hhiYxhgL7ZzRNVCtR4OYKgiDPkhUpJoL2e1uosKQ= X-Received: by 2002:a1f:1942:0:b0:49d:723f:590b with SMTP id 63-20020a1f1942000000b0049d723f590bmr2213907vkz.7.1698392884959; Fri, 27 Oct 2023 00:48:04 -0700 (PDT) MIME-Version: 1.0 References: <207cb501-558a-445b-95b5-b891819aefb6@gmail.com> <8C2D8235D4C8D5F4+20231027063748273099110@rivai.ai> In-Reply-To: From: Kito Cheng Date: Fri, 27 Oct 2023 15:47:53 +0800 Message-ID: Subject: Re: Re: [PATCH] RISC-V: Add rawmemchr expander. To: "juzhe.zhong@rivai.ai" Cc: Robin Dapp , gcc-patches , palmer , jeffreyalaw Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Could you put it into riscv-string.cc rather than riscv-v.cc? I would like to put those builtin function expander together if possible, riscv-string.cc might little bit confuse, but it's all included in string.h On Fri, Oct 27, 2023 at 3:40=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > LGTM. Thanks. > > ________________________________ > juzhe.zhong@rivai.ai > > > From: Robin Dapp > Date: 2023-10-27 15:38 > To: =E9=92=9F=E5=B1=85=E5=93=B2; gcc-patches; palmer; kito.cheng; Jeff La= w > CC: rdapp.gcc > Subject: Re: [PATCH] RISC-V: Add rawmemchr expander. > > Suggested adapt codes as follows: > > > > unsigned int element_size =3D GET_MODE_SIZE (mode).to_constant (); > > poly_int64 nunits =3D exact_div (BYTES_PER_RISCV_VECTOR *TARGET_MAX_LMU= L, element_size); > > if (!get_vector_mode(mode, nunits).exists(&vmode)) > > gcc_unreachable (); > > Actually I was initially considering using lmul =3D m8 here, > unconditionally, but the param is probably the more intuitive choice. > > Attached v2 with that included. Also moved the riscv test to > autovec/builtin/ so we can add the other builtins as well. > > > Also, this patch reminds me we are missing some more similiar builtin > > function which can use RVV: > > > > strlen, strcpy, strcmp...etc > > Yes we should still have them but I'd rather not work on that right > now. How about I open a PR for it so we can still add them in stage 3? > Their impact is pretty localized and the risk should be low. > Kito, Palmer, Jeff - would that be acceptable? > > Regards > Robin > > gcc/ChangeLog: > > * config/riscv/autovec.md (rawmemchr): New expander. > * config/riscv/riscv-protos.h (enum insn_type): Define. > (expand_rawmemchr): New function. > * config/riscv/riscv-v.cc (expand_rawmemchr): Add vectorized > rawmemchr. > * internal-fn.cc (expand_RAWMEMCHR): Fix typo. > > gcc/testsuite/ChangeLog: > > * gcc.dg/tree-ssa/ldist-rawmemchr-1.c: Add riscv. > * gcc.dg/tree-ssa/ldist-rawmemchr-2.c: Ditto. > * gcc.target/riscv/rvv/rvv.exp: Add builtin directory. > * gcc.target/riscv/rvv/autovec/builtin/rawmemchr-1.c: New test. > --- > gcc/config/riscv/autovec.md | 13 +++ > gcc/config/riscv/riscv-protos.h | 1 + > gcc/config/riscv/riscv-v.cc | 89 +++++++++++++++++ > gcc/internal-fn.cc | 2 +- > .../gcc.dg/tree-ssa/ldist-rawmemchr-1.c | 8 +- > .../gcc.dg/tree-ssa/ldist-rawmemchr-2.c | 8 +- > .../riscv/rvv/autovec/builtin/rawmemchr-1.c | 99 +++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + > 8 files changed, 213 insertions(+), 9 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/builtin/raw= memchr-1.c > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index 1ddc1993120..4f13494afdb 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -2397,3 +2397,16 @@ (define_expand "lfloor2" > DONE; > } > ) > + > +;; Implement rawmemchr[qi|si|hi]. > +(define_expand "rawmemchr" > + [(match_operand 0 "register_operand") > + (match_operand 1 "memory_operand") > + (match_operand:ANYI 2 "const_int_operand")] > + "TARGET_VECTOR" > + { > + riscv_vector::expand_rawmemchr(mode, operands[0], operands[1], > + operands[2]); > + DONE; > + } > +) > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-pro= tos.h > index 843a81b0e86..7f148ed95fe 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -526,6 +526,7 @@ void expand_cond_unop (unsigned, rtx *); > void expand_cond_binop (unsigned, rtx *); > void expand_cond_ternop (unsigned, rtx *); > void expand_popcount (rtx *); > +void expand_rawmemchr (machine_mode, rtx, rtx, rtx); > /* Rounding mode bitfield for fixed point VXRM. */ > enum fixed_point_rounding_mode > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index 3fe8125801b..0f664553cf4 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -2215,6 +2215,95 @@ expand_block_move (rtx dst_in, rtx src_in, rtx len= gth_in) > return true; > } > +/* Implement rawmemchr using vector instructions. > + It can be assumed that the needle is in the haystack, otherwise the > + behavior is undefined. */ > + > +void > +expand_rawmemchr (machine_mode mode, rtx dst, rtx src, rtx pat) > +{ > + /* > + rawmemchr: > + loop: > + vsetvli a1, zero, e[8,16,32,64], m1, ta, ma > + vle[8,16,32,64]ff.v v8, (a0) # Load. > + csrr a1, vl # Get number of bytes read. > + vmseq.vx v0, v8, pat # v0 =3D (v8 =3D=3D {pat, pat, ...}) > + vfirst.m a2, v0 # Find first hit. > + add a0, a0, a1 # Bump pointer. > + bltz a2, loop # Not found? > + > + sub a0, a0, a1 # Go back by a1. > + shll a2, a2, [0,1,2,3] # Shift to get byte offset. > + add a0, a0, a2 # Add the offset. > + > + ret > + */ > + gcc_assert (TARGET_VECTOR); > + > + unsigned int isize =3D GET_MODE_SIZE (mode).to_constant (); > + int lmul =3D riscv_autovec_lmul =3D=3D RVV_DYNAMIC ? RVV_M8 : riscv_au= tovec_lmul; > + poly_int64 nunits =3D exact_div (BYTES_PER_RISCV_VECTOR * lmul, isize)= ; > + > + machine_mode vmode; > + if (!get_vector_mode (GET_MODE_INNER (mode), nunits).exists (&vmode)) > + gcc_unreachable (); > + > + machine_mode mask_mode =3D get_mask_mode (vmode); > + > + rtx cnt =3D gen_reg_rtx (Pmode); > + rtx end =3D gen_reg_rtx (Pmode); > + rtx vec =3D gen_reg_rtx (vmode); > + rtx mask =3D gen_reg_rtx (mask_mode); > + > + /* After finding the first vector element matching the needle, we > + need to multiply by the vector element width (SEW) in order to > + return a pointer to the matching byte. */ > + unsigned int shift =3D exact_log2 (GET_MODE_SIZE (mode).to_constant ()= ); > + > + rtx src_addr =3D copy_addr_to_reg (XEXP (src, 0)); > + > + rtx loop =3D gen_label_rtx (); > + emit_label (loop); > + > + rtx vsrc =3D change_address (src, vmode, src_addr); > + > + /* Emit a first-fault load. */ > + rtx vlops[] =3D {vec, vsrc}; > + emit_vlmax_insn (code_for_pred_fault_load (vmode), UNARY_OP, vlops); > + > + /* Read how far we read. */ > + if (Pmode =3D=3D SImode) > + emit_insn (gen_read_vlsi (cnt)); > + else > + emit_insn (gen_read_vldi_zero_extend (cnt)); > + > + /* Compare needle with haystack and store in a mask. */ > + rtx eq =3D gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, pat)= , vec); > + rtx vmsops[] =3D {mask, eq, vec, pat}; > + emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode), COMPARE_OP, vms= ops, > + cnt); > + > + /* Find the first bit in the mask. */ > + rtx vfops[] =3D {end, mask}; > + emit_nonvlmax_insn (code_for_pred_ffs (mask_mode, Pmode), > + CPOP_OP, vfops, cnt); > + > + /* Bump the pointer. */ > + emit_insn (gen_rtx_SET (src_addr, gen_rtx_PLUS (Pmode, src_addr, cnt))= ); > + > + /* Emit the loop condition. */ > + rtx test =3D gen_rtx_LT (VOIDmode, end, const0_rtx); > + emit_jump_insn (gen_cbranch4 (Pmode, test, end, const0_rtx, loop)); > + > + /* We overran by CNT, subtract it. */ > + emit_insn (gen_rtx_SET (src_addr, gen_rtx_MINUS (Pmode, src_addr, cnt)= )); > + > + /* We found something at SRC + END * [1,2,4,8]. */ > + emit_insn (gen_rtx_SET (end, gen_rtx_ASHIFT (Pmode, end, GEN_INT (shif= t)))); > + emit_insn (gen_rtx_SET (dst, gen_rtx_PLUS (Pmode, src_addr, end))); > +} > + > /* Return the vectorization machine mode for RVV according to LMUL. */ > machine_mode > preferred_simd_mode (scalar_mode mode) > diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc > index ed83fa8112e..adf84f20a44 100644 > --- a/gcc/internal-fn.cc > +++ b/gcc/internal-fn.cc > @@ -3242,7 +3242,7 @@ expand_VEC_CONVERT (internal_fn, gcall *) > gcc_unreachable (); > } > -/* Expand IFN_RAWMEMCHAR internal function. */ > +/* Expand IFN_RAWMEMCHR internal function. */ > void > expand_RAWMEMCHR (internal_fn, gcall *stmt) > diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ldist-rawmemchr-1.c b/gcc/test= suite/gcc.dg/tree-ssa/ldist-rawmemchr-1.c > index bf6335f6360..adf53b10def 100644 > --- a/gcc/testsuite/gcc.dg/tree-ssa/ldist-rawmemchr-1.c > +++ b/gcc/testsuite/gcc.dg/tree-ssa/ldist-rawmemchr-1.c > @@ -1,9 +1,9 @@ > -/* { dg-do run { target s390x-*-* } } */ > +/* { dg-do run { target { { s390x-*-* } || { riscv_v } } } } */ > /* { dg-options "-O2 -ftree-loop-distribution -fdump-tree-ldist-details" = } */ > /* { dg-additional-options "-march=3Dz13 -mzarch" { target s390x-*-* } } = */ > -/* { dg-final { scan-tree-dump-times "generated rawmemchrQI" 2 "ldist" {= target s390x-*-* } } } */ > -/* { dg-final { scan-tree-dump-times "generated rawmemchrHI" 2 "ldist" {= target s390x-*-* } } } */ > -/* { dg-final { scan-tree-dump-times "generated rawmemchrSI" 2 "ldist" {= target s390x-*-* } } } */ > +/* { dg-final { scan-tree-dump-times "generated rawmemchrQI" 2 "ldist" {= target { { s390x-*-* } || { riscv_v } } } } } */ > +/* { dg-final { scan-tree-dump-times "generated rawmemchrHI" 2 "ldist" {= target { { s390x-*-* } || { riscv_v } } } } } */ > +/* { dg-final { scan-tree-dump-times "generated rawmemchrSI" 2 "ldist" {= target { { s390x-*-* } || { riscv_v } } } } } */ > /* Rawmemchr pattern: reduction stmt and no store */ > diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ldist-rawmemchr-2.c b/gcc/test= suite/gcc.dg/tree-ssa/ldist-rawmemchr-2.c > index 83f5a35a322..6c8a485a3aa 100644 > --- a/gcc/testsuite/gcc.dg/tree-ssa/ldist-rawmemchr-2.c > +++ b/gcc/testsuite/gcc.dg/tree-ssa/ldist-rawmemchr-2.c > @@ -1,9 +1,9 @@ > -/* { dg-do run { target s390x-*-* } } */ > +/* { dg-do run { target { { s390x-*-* } || { riscv_v } } } } */ > /* { dg-options "-O2 -ftree-loop-distribution -fdump-tree-ldist-details" = } */ > /* { dg-additional-options "-march=3Dz13 -mzarch" { target s390x-*-* } } = */ > -/* { dg-final { scan-tree-dump-times "generated rawmemchrQI" 2 "ldist" {= target s390x-*-* } } } */ > -/* { dg-final { scan-tree-dump-times "generated rawmemchrHI" 2 "ldist" {= target s390x-*-* } } } */ > -/* { dg-final { scan-tree-dump-times "generated rawmemchrSI" 2 "ldist" {= target s390x-*-* } } } */ > +/* { dg-final { scan-tree-dump-times "generated rawmemchrQI" 2 "ldist" {= target { { s390x-*-* } || { riscv_v } } } } } */ > +/* { dg-final { scan-tree-dump-times "generated rawmemchrHI" 2 "ldist" {= target { { s390x-*-* } || { riscv_v } } } } } */ > +/* { dg-final { scan-tree-dump-times "generated rawmemchrSI" 2 "ldist" {= target { { s390x-*-* } || { riscv_v } } } } } */ > /* Rawmemchr pattern: reduction stmt and store */ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/builtin/rawmemchr= -1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/builtin/rawmemchr-1.c > new file mode 100644 > index 00000000000..ba83cb3836f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/builtin/rawmemchr-1.c > @@ -0,0 +1,99 @@ > +/* { dg-do run { target { riscv_v } } } */ > +/* { dg-additional-options "-std=3Dgnu99 -O2 -ftree-loop-distribution -f= dump-tree-ldist-details" } */ > +/* { dg-final { scan-tree-dump-times "generated rawmemchrQI" 2 "ldist" }= } */ > +/* { dg-final { scan-tree-dump-times "generated rawmemchrHI" 2 "ldist" }= } */ > +/* { dg-final { scan-tree-dump-times "generated rawmemchrSI" 2 "ldist" }= } */ > + > +#include > +#include > +#include > +#include > + > +#define rawmemchrT(T, pattern) \ > +__attribute__((noinline,noclone)) \ > +T* rawmemchr_##T (T *s) \ > +{ \ > + while (*s !=3D pattern) \ > + ++s; \ > + return s; \ > +} > + > +rawmemchrT(int8_t, (int8_t)0xde) > +rawmemchrT(uint8_t, 0xde) > +rawmemchrT(int16_t, (int16_t)0xdead) > +rawmemchrT(uint16_t, 0xdead) > +rawmemchrT(int32_t, (int32_t)0xdeadbeef) > +rawmemchrT(uint32_t, 0xdeadbeef) > + > +#define runT(T, pattern) \ > +void run_##T () \ > +{ \ > + T *buf =3D malloc (4096 * 2 * sizeof(T)); \ > + assert (buf !=3D NULL); \ > + memset (buf, 0xa, 4096 * 2 * sizeof(T)); \ > + /* ensure q is 4096-byte aligned */ \ > + T *q =3D (T*)((unsigned char *)buf \ > + + (4096 - ((uintptr_t)buf & 4095))); \ > + T *p; \ > + /* unaligned + block boundary + 1st load */ \ > + p =3D (T *) ((uintptr_t)q - 8); \ > + p[2] =3D pattern; \ > + assert ((rawmemchr_##T (&p[0]) =3D=3D &p[2])); \ > + p[2] =3D (T) 0xaaaaaaaa; \ > + /* unaligned + block boundary + 2nd load */ \ > + p =3D (T *) ((uintptr_t)q - 8); \ > + p[6] =3D pattern; \ > + assert ((rawmemchr_##T (&p[0]) =3D=3D &p[6])); \ > + p[6] =3D (T) 0xaaaaaaaa; \ > + /* unaligned + 1st load */ \ > + q[5] =3D pattern; \ > + assert ((rawmemchr_##T (&q[2]) =3D=3D &q[5])); \ > + q[5] =3D (T) 0xaaaaaaaa; \ > + /* unaligned + 2nd load */ \ > + q[14] =3D pattern; \ > + assert ((rawmemchr_##T (&q[2]) =3D=3D &q[14])); \ > + q[14] =3D (T) 0xaaaaaaaa; \ > + /* unaligned + 3rd load */ \ > + q[19] =3D pattern; \ > + assert ((rawmemchr_##T (&q[2]) =3D=3D &q[19])); \ > + q[19] =3D (T) 0xaaaaaaaa; \ > + /* unaligned + 4th load */ \ > + q[25] =3D pattern; \ > + assert ((rawmemchr_##T (&q[2]) =3D=3D &q[25])); \ > + q[25] =3D (T) 0xaaaaaaaa; \ > + /* aligned + 1st load */ \ > + q[5] =3D pattern; \ > + assert ((rawmemchr_##T (&q[0]) =3D=3D &q[5])); \ > + q[5] =3D (T) 0xaaaaaaaa; \ > + /* aligned + 2nd load */ \ > + q[14] =3D pattern; \ > + assert ((rawmemchr_##T (&q[0]) =3D=3D &q[14])); \ > + q[14] =3D (T) 0xaaaaaaaa; \ > + /* aligned + 3rd load */ \ > + q[19] =3D pattern; \ > + assert ((rawmemchr_##T (&q[0]) =3D=3D &q[19])); \ > + q[19] =3D (T) 0xaaaaaaaa; \ > + /* aligned + 4th load */ \ > + q[25] =3D pattern; \ > + assert ((rawmemchr_##T (&q[0]) =3D=3D &q[25])); \ > + q[25] =3D (T) 0xaaaaaaaa; \ > + free (buf); \ > +} > + > +runT(int8_t, (int8_t)0xde) > +runT(uint8_t, 0xde) > +runT(int16_t, (int16_t)0xdead) > +runT(uint16_t, 0xdead) > +runT(int32_t, (int32_t)0xdeadbeef) > +runT(uint32_t, 0xdeadbeef) > + > +int main (void) > +{ > + run_uint8_t (); > + run_int8_t (); > + run_uint16_t (); > + run_int16_t (); > + run_uint32_t (); > + run_int32_t (); > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/g= cc.target/riscv/rvv/rvv.exp > index b19aa7b4ae6..9f7a10d5b78 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > @@ -81,6 +81,8 @@ foreach op $AUTOVEC_TEST_OPTS { > "" "$op" > dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/cond/*.\[c= S\]]] \ > "" "$op" > + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/builtin/*.= \[cS\]]] \ > + "" "$op" > } > # widening operation only test on LMUL < 8 > -- > 2.41.0 > >