From: Kito Cheng <kito.cheng@gmail.com>
To: Lehua Ding <lehua.ding@rivai.ai>
Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai
Subject: Re: [PATCH V5 0/3] RISC-V: Add an experimental vector calling convention
Date: Tue, 5 Sep 2023 16:18:45 +0800 [thread overview]
Message-ID: <CA+yXCZAmRERSAKpQJxJRacfU+y8NvbQfCtD=Y4t+izZ==od1Cw@mail.gmail.com> (raw)
In-Reply-To: <20230905074452.3714603-1-lehua.ding@rivai.ai>
Thanks for fixing the issue! I guess I could find time tonight to do
the final round review and test :P then we could land this patch this
week.
On Tue, Sep 5, 2023 at 3:45 PM Lehua Ding <lehua.ding@rivai.ai> wrote:
>
> V5 change: Rebase and fix vsetvl testcase fail by change
> `(unspec [...] UNSPEC_CALLEE_CC)` to `(use (unspec [...] UNSPEC_CALLEE_CC))`.
> This change makes single_set function re-think call_insn as a
> single set pattern.
>
> Hi RISC-V folks,
>
> This patch implement the proposal of RISC-V vector calling convention[1] and
> this feature can be enabled by `--param=riscv-vector-abi` option. Currently,
> all vector type arguments and return values are pass by reference. With this
> patch, these arguments and return values can pass through vector registers.
> Currently only vector types defined in the RISC-V Vector Extension Intrinsic Document[2]
> are supported. GNU-ext vector types are unsupported for now since the
> corresponding proposal was not presented.
>
> The proposal introduce a new calling convention variant, functions which follow
> this variant need follow the bellow vector register convention.
>
> | Name | ABI Mnemonic | Meaning | Preserved across calls?
> =================================================================================
> | v0 | | Argument register | No
> | v1-v7 | | Callee-saved registers | Yes
> | v8-v23 | | Argument registers | No
> | v24-v31 | | Callee-saved registers | Yes
>
> If a functions follow this vector calling convention, then the function symbole
> must be annotated with .variant_cc directive[3] (used to indicate that it is a
> calling convention variant).
>
> This implementation split into three parts, each part corresponds to a sub-patch.
>
> - Part-1: Select suitable vector regsiters for vector type arguments and return
> values according to the proposal.
> - Part-2: Allocate frame area for callee-saved vector registers and save/restore
> them in prologue and epilogue.
> - Part-3: Generate .variant_cc directive for vector function in assembly code.
>
> [1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389
> [2] https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#type-system
> [3] https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops
>
> Best,
> Lehua
>
> Lehua Ding (3):
> RISC-V: Part-1: Select suitable vector registers for vector type args
> and returns
> RISC-V: Part-2: Save/Restore vector registers which need to be
> preversed
> RISC-V: Part-3: Output .variant_cc directive for vector function
>
> gcc/config/riscv/riscv-protos.h | 4 +
> gcc/config/riscv/riscv-sr.cc | 8 +-
> gcc/config/riscv/riscv-vector-builtins.cc | 10 +
> gcc/config/riscv/riscv.cc | 484 ++++++++++++++++--
> gcc/config/riscv/riscv.h | 43 ++
> gcc/config/riscv/riscv.md | 51 +-
> gcc/config/riscv/riscv.opt | 5 +
> .../riscv/rvv/base/abi-call-args-1-run.c | 127 +++++
> .../riscv/rvv/base/abi-call-args-1.c | 197 +++++++
> .../riscv/rvv/base/abi-call-args-2-run.c | 34 ++
> .../riscv/rvv/base/abi-call-args-2.c | 27 +
> .../riscv/rvv/base/abi-call-args-3-run.c | 260 ++++++++++
> .../riscv/rvv/base/abi-call-args-3.c | 116 +++++
> .../riscv/rvv/base/abi-call-args-4-run.c | 145 ++++++
> .../riscv/rvv/base/abi-call-args-4.c | 111 ++++
> .../riscv/rvv/base/abi-call-error-1.c | 11 +
> .../riscv/rvv/base/abi-call-return-run.c | 127 +++++
> .../riscv/rvv/base/abi-call-return.c | 197 +++++++
> .../riscv/rvv/base/abi-call-variant_cc.c | 39 ++
> .../rvv/base/abi-callee-saved-1-fixed-1.c | 86 ++++
> .../rvv/base/abi-callee-saved-1-fixed-2.c | 86 ++++
> .../base/abi-callee-saved-1-save-restore.c | 85 +++
> .../riscv/rvv/base/abi-callee-saved-1-zcmp.c | 85 +++
> .../riscv/rvv/base/abi-callee-saved-1.c | 88 ++++
> .../base/abi-callee-saved-2-save-restore.c | 108 ++++
> .../riscv/rvv/base/abi-callee-saved-2-zcmp.c | 107 ++++
> .../riscv/rvv/base/abi-callee-saved-2.c | 117 +++++
> 27 files changed, 2709 insertions(+), 49 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c
>
> --
> 2.36.3
>
next prev parent reply other threads:[~2023-09-05 8:18 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-05 7:44 Lehua Ding
2023-09-05 7:44 ` [PATCH V5 1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns Lehua Ding
2023-09-05 7:44 ` [PATCH V5 2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed Lehua Ding
2023-09-05 7:44 ` [PATCH V5 3/3] RISC-V: Part-3: Output .variant_cc directive for vector function Lehua Ding
2023-09-05 8:18 ` Kito Cheng [this message]
2023-09-06 8:23 ` [PATCH V5 0/3] RISC-V: Add an experimental vector calling convention Kito Cheng
2023-09-08 6:28 ` Lehua Ding
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