From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by sourceware.org (Postfix) with ESMTPS id 94944385800A for ; Wed, 18 Nov 2020 05:44:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 94944385800A Received: by mail-wm1-x342.google.com with SMTP id c9so1775500wml.5 for ; Tue, 17 Nov 2020 21:44:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=L7cPkoCDQrpFLTOn41ST2eCwf2Ekk72cYj7Fpu80Wh0=; b=DzOETJVD8V4hRHkfeW4rutbEZ/VRIjtUI4OXCzBfC93ukC8OYRPsqCpP9qN27DLvVL +WFTX9zuGl113NLDEst/4/Q4FhSv9iDNEbwAoSEwlqBqHuBCIVuc3D+mRlDprsXSj5Tm xgnsHekrXnPW/r3CeQrfUNt4bGlMQz+jmmEhBrDvgav/XL7C4PGgwA1dS8R/2hVLVYPG rxZVxFIp9DdeQaXLafVc1J1kX1AxvPtq4JRtx5I9YKLlhupROPpYCNfwY257Vjj7USHY 3iGfSMfjKmR00TOEiUhQXJNl+ZdVJlJxrk4f/mnbA3k84oK6Fq3OBVYF1jP3DqgIZ2Zk vT5w== X-Gm-Message-State: AOAM530/oXNvvUA1EuKW3tpXJ6iIRMAsQZfSR14Xw0lDndqu/yAgjmKL FJ/ULF0SRy5D0hdpj+P1MgTRt0jNnYx0Rhpb0HjBddqfaJU= X-Google-Smtp-Source: ABdhPJzWgNcCP86nXxSlIh6R8nyjMLpCYHQcx2uxGpFhGrbFb46h4sQ+C8kTIu4nWDelmEFSMxidz6U1YlQQtqF0Vrg= X-Received: by 2002:a1c:4b18:: with SMTP id y24mr2609987wma.154.1605678280591; Tue, 17 Nov 2020 21:44:40 -0800 (PST) MIME-Version: 1.0 References: <20201113072910.42353-1-kito.cheng@sifive.com> <20201113072910.42353-3-kito.cheng@sifive.com> In-Reply-To: From: Kito Cheng Date: Wed, 18 Nov 2020 13:44:29 +0800 Message-ID: Subject: Re: [PATCH 2/3] RISC-V: Support zicsr and zifencei extension for -march. To: Jim Wilson Cc: Kito Cheng , GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Nov 2020 05:44:42 -0000 >> - CSR related instructions and fence instructions has to be splitted from >> baseline ISA, zicsr and zifencei are corresponding sub-extension. > > > It is actually only fence.i that is split off. fence is still part of the base ISA. This is why it is called zifencei. Oh...I didn't notice that, thanks for the review. >> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c >> index 738556539f6..2aaa8e96451 100644 >> --- a/gcc/config/riscv/riscv.c >> +++ b/gcc/config/riscv/riscv.c >> @@ -3337,6 +3337,9 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) >> static bool >> riscv_memmodel_needs_release_fence (enum memmodel model) >> { >> + if (!TARGET_ZIFENCEI) >> + return false; >> + >> switch (model) >> { >> case MEMMODEL_ACQ_REL: > > > This part looks wrong, as riscv_memmodel_needs_release_fence is only used for fence instructions, not for fence.i. >> >> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md >> index f15bad3b29e..756b35fb8c0 100644 >> --- a/gcc/config/riscv/riscv.md >> +++ b/gcc/config/riscv/riscv.md >> @@ -1543,19 +1543,20 @@ >> LCT_NORMAL, VOIDmode, operands[0], Pmode, >> operands[1], Pmode, const0_rtx, Pmode); >> #else >> - emit_insn (gen_fence_i ()); >> + if (TARGET_ZIFENCEI) >> + emit_insn (gen_fence_i ()); >> #endif >> DONE; >> }) >> >> (define_insn "fence" >> [(unspec_volatile [(const_int 0)] UNSPECV_FENCE)] >> - "" >> + "TARGET_ZIFENCEI" >> "%|fence%-") >> >> (define_insn "fence_i" >> [(unspec_volatile [(const_int 0)] UNSPECV_FENCE_I)] >> - "" >> + "TARGET_ZIFENCEI" >> "fence.i") >> >> ;; > > > The fence_i and clear_cache patterns are OK. The fence pattern change is wrong. > > You didn't change sync.md, but it only uses fence, so it needs no change. > > Jim >