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From: Kito Cheng <kito.cheng@gmail.com>
To: yanzhang.wang@intel.com
Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai,
	kito.cheng@sifive.com,  pan2.li@intel.com
Subject: Re: [PATCH v2] RISC-V: Fix regression of -fzero-call-used-regs=all
Date: Fri, 7 Apr 2023 15:07:51 +0800	[thread overview]
Message-ID: <CA+yXCZAoY2jpZB3dOv_v5T562ECMjTaLaj=s9iHDrHYPBUBTsQ@mail.gmail.com> (raw)
In-Reply-To: <20230407065940.2331101-1-yanzhang.wang@intel.com>

Generally LGTM, just one more comment :)

> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 2e91d019f6c..aad046240ee 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -724,4 +735,54 @@ gen_avl_for_scalar_move (rtx avl)
>      }
>  }
>
> +HARD_REG_SET
> +vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)

I would prefer this should be moved to riscv.cc too, major concern is
we don't want to introduce `hard-reg-set.h` into riscv-protos.h.

  reply	other threads:[~2023-04-07  7:08 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-06 13:34 [PATCH] " yanzhang.wang
2023-04-06 13:47 ` juzhe.zhong
2023-04-06 14:59   ` Kito Cheng
2023-04-07  6:59 ` [PATCH v2] " yanzhang.wang
2023-04-07  7:07   ` Kito Cheng [this message]
2023-04-07 12:32 ` [PATCH v3] " yanzhang.wang
2023-04-08 18:39   ` Jeff Law
2023-04-10  2:21     ` Wang, Yanzhang
2023-04-10  3:11       ` Kito Cheng
2023-04-10 20:57         ` Jeff Law
2023-04-10  3:00 ` [PATCH v4] " yanzhang.wang
2023-04-11 11:37 ` [PATCH v5] " yanzhang.wang
2023-04-11 12:00   ` Wang, Yanzhang
2023-04-11 14:11     ` Kito Cheng

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