From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by sourceware.org (Postfix) with ESMTPS id AB3393834F06 for ; Thu, 1 Sep 2022 02:06:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AB3393834F06 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x533.google.com with SMTP id t5so20660431edc.11 for ; Wed, 31 Aug 2022 19:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=4Mv9BR81tyzqJfcjgRmWgFiHQpdEGNge+R1KIcy4MyA=; b=YIonFVsUagiKKxodvDL1Qes2gTIBIa6KkXC7ILUYBHOZKySMTkvwL5phjkyixa4Q1B LtNr0RVQmIC/Sk6oZ2L0Ubs5UxtOfufY9DFM4NsgOA0q78SkLofBSjzzYBPYFyuFVHH3 I9ZLzUszWwwZA5jOnHK9UqiynO2TFVOZctBHj+QYs4IM60KNnmvyKhafrz0MwsUSpkwZ D2mEpBsN0GE2Eja88foF/GHFam1ykM4MiED17NIUNTdRw2hCuUW7+/OjaRWOZ6eajYsN KN6SsQuqwEj8wi7f573dzMGqeoYIIlmli7MoDaMWHs18bbs+ABgjs5o5N3tTpBPiCPSX opDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=4Mv9BR81tyzqJfcjgRmWgFiHQpdEGNge+R1KIcy4MyA=; b=IWqtgWDJXNteX3dW3/33BnZP4ilQv0/y51n1Au/T+4oDPhL3rEXVgEOkdzpKIHBu7E H//uI6HgjM/FuzedEBIjQBczqbpvKSacQQ12+5bF96fS/CwwZ4PYBIWv+LzMKauMLIkC pDbRCm4V8J5Fs+CYkM4RMQSegrr++NRjYyjwO5PyyV/m6W+jOgjJsKfufaYzDxzH60LE Rg2a7Xct9Ttqlh23LLIl9sBAhVKc+JvzBRDb6Re4sBYF8Qxgmholbi+qQu79SNFiYmv9 uNJgTqmSNj4Igx7Topce3S+zXJLmODO9DSOWRVhlXRhMm0z7SWvgDZcd/uITzxExqTeX vuNA== X-Gm-Message-State: ACgBeo3QUFxHKdX2USO/UXDZMt+L6JTHRpHPgflDMjejzbxsZh0xHtm4 bURHDsZNdSi2xPv4qixM21k3CqW9l2FbFh1VvQlXkfM4KfQ= X-Google-Smtp-Source: AA6agR4P9e153SF679jEtyV11diHMtwNPPVIs1qgIxSmFLY9cywLZPabgz0QSNg3hJZA3Wo6Ma1MD7FYf5W2bJgkw3c= X-Received: by 2002:a05:6402:1943:b0:443:5ffb:b04e with SMTP id f3-20020a056402194300b004435ffbb04emr2210699edz.230.1661997980454; Wed, 31 Aug 2022 19:06:20 -0700 (PDT) MIME-Version: 1.0 References: <20220830061351.19655-1-juzhe.zhong@rivai.ai> In-Reply-To: <20220830061351.19655-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Thu, 1 Sep 2022 10:06:08 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add RVV constraints. To: juzhe.zhong@rivai.ai Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Thanks, committed! On Tue, Aug 30, 2022 at 2:15 PM wrote: > > From: zhongjuzhe > > gcc/ChangeLog: > > * config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Add "vr" constraint. > (TARGET_VECTOR ? VD_REGS : NO_REGS): Add "vd" constraint. > (TARGET_VECTOR ? VM_REGS : NO_REGS): Add "vm" constraint. > (vp): Add poly constraint. > > --- > gcc/config/riscv/constraints.md | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md > index 2873d533cb5..669e5ed734b 100644 > --- a/gcc/config/riscv/constraints.md > +++ b/gcc/config/riscv/constraints.md > @@ -108,3 +108,23 @@ > A constant @code{move_operand}." > (and (match_operand 0 "move_operand") > (match_test "CONSTANT_P (op)"))) > + > +;; Vector constraints. > + > +(define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS" > + "A vector register (if available).") > + > +(define_register_constraint "vd" "TARGET_VECTOR ? VD_REGS : NO_REGS" > + "A vector register except mask register (if available).") > + > +(define_register_constraint "vm" "TARGET_VECTOR ? VM_REGS : NO_REGS" > + "A vector mask register (if available).") > + > +;; This constraint is used to match instruction "csrr %0, vlenb" which is generated in "mov". > +;; VLENB is a run-time constant which represent the vector register length in bytes. > +;; BYTES_PER_RISCV_VECTOR represent runtime invariant of vector register length in bytes. > +;; We should only allow the poly equal to BYTES_PER_RISCV_VECTOR. > +(define_constraint "vp" > + "POLY_INT" > + (and (match_code "const_poly_int") > + (match_test "known_eq (rtx_to_poly_int64 (op), BYTES_PER_RISCV_VECTOR)"))) > \ No newline at end of file > -- > 2.36.1 >