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From: Kito Cheng <kito.cheng@gmail.com>
Date: Wed, 26 Apr 2023 21:23:52 +0800
Message-ID: <CA+yXCZArGnkohV7GFLQF3h16qmU3SDUnjupx150QfQJFk+uRxw@mail.gmail.com>
Subject: Re: [PATCH] RISC-V: Legitimise the const0_rtx for RVV load/store address
To: pan2.li@intel.com
Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, kito.cheng@sifive.com, 
	yanzhang.wang@intel.com
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List-Id: <gcc-patches.gcc.gnu.org>

LGTM, pushed to trunk

> This patch try to legitimise the const0_rtx (aka zero register)
> as the base register for the RVV load/store instructions.
>
> For example:
> vint32m1_t test_vle32_v_i32m1_shortcut (size_t vl)
> {
>   return __riscv_vle32_v_i32m1 ((int32_t *)0, vl);
> }

The example is kind of counter intuitive to me, I know it's legal from
ISA spec level, but can't understand why it's useful...until I saw you
mention auto vec and index load - I realized this is optimization for
gather/scatter code gen.