From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe29.google.com (mail-vs1-xe29.google.com [IPv6:2607:f8b0:4864:20::e29]) by sourceware.org (Postfix) with ESMTPS id 9EC823858D32 for ; Tue, 18 Apr 2023 18:21:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9EC823858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe29.google.com with SMTP id f39so2420399vsv.4 for ; Tue, 18 Apr 2023 11:21:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681842112; x=1684434112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=hyeC2kBMlr+6ZvDO7cnIzZP9os8GAMZPZUT0bamZc2k=; b=THejxVWbbCkYnP4V/sTMzane6bEF4/3DG6VQWmx2AOmNy7mMaahhjhYpmDU9+87fR3 uHXX/AKCWnl+qVzTF4RHXwXUw3cKC3Y6a2N4X+1RnFaDSqNF0lmH7OLcNivQJQ80V4h2 oZKcWI9HfJznSFNBkJclY5PCQR8G8RKJFuOkTeqWsydCAMSO2q+sbBjxQ1qOStReNmKy WmktvAE9ciDlEza2e5qNTD1PDtYyWMBogWb86aDWaRI6boj2A1Tsflu+vZtWKs9sYT53 jOoErFRzxDwogRIPKacHi5pY6VYXkKdGoko4cV5iZU6wCVgHQbmV0KKUl2Ju2lQOZx+A 2SaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681842112; x=1684434112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hyeC2kBMlr+6ZvDO7cnIzZP9os8GAMZPZUT0bamZc2k=; b=AGqcv0psdgHFQW9w9zoNlyhTz73/Gdml0fUB+vbG90naJAoTWNg4HfnZjNG1hqF2B4 kOIsWtdbZICzQINJW7VaAeh26GIR3e+I7ENFQH1XL7hmj+RyDfnzcP/7b8LtcqZwLFw4 dzLuCyGolDSsIA9/qOaj6RBGOnEyQpj8d9MRNfoosh20yJuxDu05u6AY1j9rZCi8EGil d126n+HVHEKo2NN73TMo7FiB2lBX4S4+Y7nMXEeiO1dymrbXwd0Do9nL2yuCCDvxyJl0 6CGfyK5FPuoBm6thtRUN7ty9lUBUl9nbSilU1+Xz9g0Iu/5DMxZc2ZCZfcewV9a0auCC 8ZJQ== X-Gm-Message-State: AAQBX9cPrN27+j6YanEUny5b11D+c2Zup9sYW99IOhkAqG1+CR66d56j IpCAmk3d/JqOIWxl0cnLt+8CxrNfcChP2GGy5LE= X-Google-Smtp-Source: AKy350ZafwPeTfluHJxD/ir/VZewCiexutjE85UAAYT9yBAO+ADon6JVK81MkKa8d7NCpvWsDR8kcWsHcPfQKCdXn8c= X-Received: by 2002:a67:facc:0:b0:426:70c:13d9 with SMTP id g12-20020a67facc000000b00426070c13d9mr6923819vsq.28.1681842111752; Tue, 18 Apr 2023 11:21:51 -0700 (PDT) MIME-Version: 1.0 References: <20230417183701.2249183-1-collison@rivosinc.com> <20230417183701.2249183-8-collison@rivosinc.com> In-Reply-To: From: Kito Cheng Date: Wed, 19 Apr 2023 02:21:40 +0800 Message-ID: Subject: Re: [PATCH v4 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2. To: Richard Biener , Jeff Law , Palmer Dabbelt Cc: Michael Collison , gcc-patches@gcc.gnu.org, =?UTF-8?B?6ZKf5bGF5ZOy?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Few more background about RVV: RISC-V has provide different VLEN configuration by different ISA extension like `zve32x`, `zve64x` and `v` zve32x just guarantee the minimal VLEN is 32 bits, zve64x guarantee the minimal VLEN is 64 bits, and v guarantee the minimal VLEN is 128 bits, Current status (without that patch): Zve32x: Mode for one vector register mode is VNx1SImode and VNx1DImode is invalid mode - one vector register could hold 1 + 1x SImode where x is 0~n, so it might hold just one SI Zve64x: Mode for one vector register mode is VNx1DImode or VNx2SImode - one vector register could hold 1 + 1x DImode where x is 0~n, so it might hold just one DI - one vector register could hold 2 + 2x SImode where x is 0~n, so it might hold just two SI So what I want to say here is VNx1DImode is really NOT safe to assume to have more than two DI in theory. However `v` extension guarantees the minimal VLEN is 128 bits. We are trying to introduce another type/mode mapping for this configure: v: Mode for one vector register mode is VNx2DImode or VNx4SImode - one vector register could hold 2 + 2x DImode where x is 0~n, so it will hold at least two DI - one vector register could hold 4 + 4x SImode where x is 0~n, so it will hold at least four DI So GET_MODE_NUNITS for a single vector register with DI mode will become 2 (VNx2DImode) if it is really possible, which is a more precise way to model the vector extension for RISC-V . On Tue, Apr 18, 2023 at 10:28=E2=80=AFPM Kito Cheng = wrote: > > Wait, VNx1DImode can be really evaluate to just one element if > -march=3Drv64g_zve64x, > > I thinks this should be just fixed on backend by this patch: > > https://patchwork.ozlabs.org/project/gcc/patch/20230414014518.15458-1-juz= he.zhong@rivai.ai/ > > On Tue, Apr 18, 2023 at 2:12=E2=80=AFPM Richard Biener via Gcc-patches > wrote: > > > > On Mon, Apr 17, 2023 at 8:42=E2=80=AFPM Michael Collison wrote: > > > > > > While working on autovectorizing for the RISCV port I encountered an = issue > > > where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is = a > > > evenly divisible by two. The RISC-V target has vector modes (e.g. VNx= 1DImode), > > > where GET_MODE_NUNITS is equal to one. > > > > > > Tested on RISCV and x86_64-linux-gnu. Okay? > > > > OK. > > > > > 2023-03-09 Michael Collison > > > > > > * tree-vect-slp.cc (can_duplicate_and_interleave_p): > > > Check that GET_MODE_NUNITS is a multiple of 2. > > > --- > > > gcc/tree-vect-slp.cc | 7 +++++-- > > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > > > diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc > > > index d73deaecce0..a64fe454e19 100644 > > > --- a/gcc/tree-vect-slp.cc > > > +++ b/gcc/tree-vect-slp.cc > > > @@ -423,10 +423,13 @@ can_duplicate_and_interleave_p (vec_info *vinfo= , unsigned int count, > > > (GET_MODE_BITSIZE (int_mode), 1); > > > tree vector_type > > > =3D get_vectype_for_scalar_type (vinfo, int_type, count); > > > + poly_int64 half_nelts; > > > if (vector_type > > > && VECTOR_MODE_P (TYPE_MODE (vector_type)) > > > && known_eq (GET_MODE_SIZE (TYPE_MODE (vector_type)), > > > - GET_MODE_SIZE (base_vector_mode))) > > > + GET_MODE_SIZE (base_vector_mode)) > > > + && multiple_p (GET_MODE_NUNITS (TYPE_MODE (vector_type)= ), > > > + 2, &half_nelts)) > > > { > > > /* Try fusing consecutive sequences of COUNT / NVECTORS= elements > > > together into elements of type INT_TYPE and using th= e result > > > @@ -434,7 +437,7 @@ can_duplicate_and_interleave_p (vec_info *vinfo, = unsigned int count, > > > poly_uint64 nelts =3D GET_MODE_NUNITS (TYPE_MODE (vecto= r_type)); > > > vec_perm_builder sel1 (nelts, 2, 3); > > > vec_perm_builder sel2 (nelts, 2, 3); > > > - poly_int64 half_nelts =3D exact_div (nelts, 2); > > > + > > > for (unsigned int i =3D 0; i < 3; ++i) > > > { > > > sel1.quick_push (i); > > > -- > > > 2.34.1 > > >