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From: Kito Cheng <kito.cheng@gmail.com>
To: Monk Chiang <monk.chiang@sifive.com>
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 1/2] RISC-V: Recognized zihintntl extensions
Date: Fri, 14 Jul 2023 15:11:36 +0800	[thread overview]
Message-ID: <CA+yXCZAsf+nCvMjxsG6PtmdOE9Y1MQYjq0jQBqtp4+bKKb=Kug@mail.gmail.com> (raw)
In-Reply-To: <20230713053856.101950-1-monk.chiang@sifive.com>

Committed, thanks :)

On Thu, Jul 13, 2023 at 1:39 PM Monk Chiang via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
>     gcc/ChangeLog:
>
>             * common/config/riscv/riscv-common.cc:
>             (riscv_implied_info): Add zihintntl item.
>             (riscv_ext_version_table): Ditto.
>             (riscv_ext_flag_table): Ditto.
>             * config/riscv/riscv-opts.h (MASK_ZIHINTNTL): New macro.
>             (TARGET_ZIHINTNTL): Ditto.
>
>     gcc/testsuite/ChangeLog:
>
>             * gcc.target/riscv/arch-22.c: New test.
>             * gcc.target/riscv/predef-28.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc    |  4 ++
>  gcc/config/riscv/riscv-opts.h              |  2 +
>  gcc/testsuite/gcc.target/riscv/arch-22.c   |  5 +++
>  gcc/testsuite/gcc.target/riscv/predef-28.c | 47 ++++++++++++++++++++++
>  4 files changed, 58 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-28.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 6091d8f281b..28c8f0c1489 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -206,6 +206,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"zksh",  ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zkt",   ISA_SPEC_CLASS_NONE, 1, 0},
>
> +  {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0},
> +
>    {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1267,6 +1269,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"zksh",   &gcc_options::x_riscv_zk_subext, MASK_ZKSH},
>    {"zkt",    &gcc_options::x_riscv_zk_subext, MASK_ZKT},
>
> +  {"zihintntl", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTNTL},
> +
>    {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ},
>    {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM},
>    {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index cfcf608ea62..beee241aa1b 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -101,9 +101,11 @@ enum riscv_entity
>
>  #define MASK_ZICSR    (1 << 0)
>  #define MASK_ZIFENCEI (1 << 1)
> +#define MASK_ZIHINTNTL (1 << 2)
>
>  #define TARGET_ZICSR    ((riscv_zi_subext & MASK_ZICSR) != 0)
>  #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
> +#define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0)
>
>  #define MASK_ZAWRS   (1 << 0)
>  #define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-22.c b/gcc/testsuite/gcc.target/riscv/arch-22.c
> new file mode 100644
> index 00000000000..cdc18e13d0f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-22.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv64gc_zihintntl -mabi=lp64 -mcmodel=medlow" } */
> +int foo()
> +{
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-28.c b/gcc/testsuite/gcc.target/riscv/predef-28.c
> new file mode 100644
> index 00000000000..81fdad571e7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-28.c
> @@ -0,0 +1,47 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_zihintntl -mabi=lp64 -mcmodel=medlow" } */
> +
> +int main () {
> +
> +#ifndef __riscv_arch_test
> +#error "__riscv_arch_test"
> +#endif
> +
> +#if __riscv_xlen != 64
> +#error "__riscv_xlen"
> +#endif
> +
> +#if !defined(__riscv_i)
> +#error "__riscv_i"
> +#endif
> +
> +#if !defined(__riscv_c)
> +#error "__riscv_c"
> +#endif
> +
> +#if defined(__riscv_e)
> +#error "__riscv_e"
> +#endif
> +
> +#if !defined(__riscv_a)
> +#error "__riscv_a"
> +#endif
> +
> +#if !defined(__riscv_m)
> +#error "__riscv_m"
> +#endif
> +
> +#if !defined(__riscv_f)
> +#error "__riscv_f"
> +#endif
> +
> +#if !defined(__riscv_d)
> +#error "__riscv_d"
> +#endif
> +
> +#if !defined(__riscv_zihintntl)
> +#error "__riscv_zihintntl"
> +#endif
> +
> +  return 0;
> +}
> --
> 2.40.1
>

      parent reply	other threads:[~2023-07-14  7:11 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-13  5:38 Monk Chiang
2023-07-13  5:38 ` [PATCH 2/2] RISC-V: Implement locality for __builtin_prefetch Monk Chiang
2023-07-14  7:13   ` Kito Cheng
2023-07-14  7:11 ` Kito Cheng [this message]

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