Lgtm too :)

钟居哲 <juzhe.zhong@rivai.ai> 於 2023年6月12日 週一 05:48 寫道：

> LGTM
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-06-11 08:33
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang;
> kito.cheng
> Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API
> From: Pan Li <pan2.li@intel.com>
>
> This patch support the intrinsic API of FP16 ZVFHMIN vlmul ext. Aka:
>
> vfloat16*_t <==> vfloat16*_t.
>
> From the user's perspective, it is reasonable to do some type convert
> between vfloat16*_t and vfloat16*_t when only ZVFHMIN is enabled.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-types.def
> (vfloat16mf4_t): Add type to X2/X4/X8/X16/X32 vlmul ext ops.
> (vfloat16mf2_t): Ditto.
> (vfloat16m1_t): Ditto.
> (vfloat16m2_t): Ditto.
> (vfloat16m4_t): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new test cases.
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add new test cases.
> ---
> .../riscv/riscv-vector-builtins-types.def     | 15 ++++++
> .../riscv/rvv/base/zvfh-over-zvfhmin.c        | 18 +++++--
> .../riscv/rvv/base/zvfhmin-intrinsic.c        | 54 +++++++++++++++++--
> 3 files changed, 79 insertions(+), 8 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def
> b/gcc/config/riscv/riscv-vector-builtins-types.def
> index 589ea532727..db8e61fea6a 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -978,6 +978,11 @@ DEF_RVV_X2_VLMUL_EXT_OPS (vuint32m4_t, 0)
> DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
> DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
> DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
> +DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 |
> RVV_REQUIRE_MIN_VLEN_64)
> +DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
> DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 |
> RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
> DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
> @@ -1014,6 +1019,10 @@ DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m1_t, 0)
> DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m2_t, 0)
> DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
> DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
> +DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 |
> RVV_REQUIRE_MIN_VLEN_64)
> +DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
> DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 |
> RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
> DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
> @@ -1040,6 +1049,9 @@ DEF_RVV_X8_VLMUL_EXT_OPS (vuint16m1_t, 0)
> DEF_RVV_X8_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X8_VLMUL_EXT_OPS (vuint32m1_t, 0)
> DEF_RVV_X8_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
> +DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 |
> RVV_REQUIRE_MIN_VLEN_64)
> +DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
> DEF_RVV_X8_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 |
> RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X8_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
> DEF_RVV_X8_VLMUL_EXT_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
> @@ -1056,6 +1068,8 @@ DEF_RVV_X16_VLMUL_EXT_OPS (vuint8mf2_t, 0)
> DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf2_t, 0)
> DEF_RVV_X16_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
> +DEF_RVV_X16_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 |
> RVV_REQUIRE_MIN_VLEN_64)
> +DEF_RVV_X16_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
> DEF_RVV_X16_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 |
> RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X32_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
> @@ -1064,6 +1078,7 @@ DEF_RVV_X32_VLMUL_EXT_OPS (vint16mf4_t,
> RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf4_t, 0)
> DEF_RVV_X32_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
> +DEF_RVV_X32_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 |
> RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X64_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X64_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> index d5bcdd5156a..ff9e0156a68 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> @@ -37,13 +37,23 @@ vuint16m8_t
> test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) {
>    return __riscv_vreinterpret_v_f16m8_u16m8(src);
> }
> +vfloat16mf2_t test_vlmul_ext_v_f16mf4_f16mf2(vfloat16mf4_t op1) {
> +  return __riscv_vlmul_ext_v_f16mf4_f16mf2(op1);
> +}
> +
> +vfloat16m8_t test_vlmul_ext_v_f16mf4_f16m8(vfloat16mf4_t op1) {
> +  return __riscv_vlmul_ext_v_f16mf4_f16m8(op1);
> +}
> +
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 6 } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> /* { dg-final { scan-assembler-times
> {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
> /* { dg-final { scan-assembler-times
> {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
> -/* { dg-final { scan-assembler-times
> {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
> -/* { dg-final { scan-assembler-times
> {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> +/* { dg-final { scan-assembler-times
> {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 6 } } */
> +/* { dg-final { scan-assembler-times
> {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> /* { dg-final { scan-assembler-times
> {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
> -/* { dg-final { scan-assembler-times
> {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> +/* { dg-final { scan-assembler-times
> {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> index e56b2751d4c..68720e64926 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -85,16 +85,62 @@ vuint16m8_t
> test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) {
>    return __riscv_vreinterpret_v_f16m8_u16m8(src);
> }
> +vfloat16mf2_t test_vlmul_ext_v_f16mf4_f16mf2(vfloat16mf4_t op1) {
> +  return __riscv_vlmul_ext_v_f16mf4_f16mf2(op1);
> +}
> +
> +vfloat16m8_t test_vlmul_ext_v_f16m4_f16m8(vfloat16m4_t op1) {
> +  return __riscv_vlmul_ext_v_f16m4_f16m8(op1);
> +}
> +
> +vfloat16m1_t test_vlmul_ext_v_f16mf4_f16m1(vfloat16mf4_t op1) {
> +  return __riscv_vlmul_ext_v_f16mf4_f16m1(op1);
> +}
> +
> +vfloat16m8_t test_vlmul_ext_v_f16m2_f16m8(vfloat16m2_t op1) {
> +  return __riscv_vlmul_ext_v_f16m2_f16m8(op1);
> +}
> +
> +vfloat16m2_t test_vlmul_ext_v_f16mf4_f16m2(vfloat16mf4_t op1) {
> +  return __riscv_vlmul_ext_v_f16mf4_f16m2(op1);
> +}
> +
> +vfloat16m8_t test_vlmul_ext_v_f16m1_f16m8(vfloat16m1_t op1) {
> +  return __riscv_vlmul_ext_v_f16m1_f16m8(op1);
> +}
> +
> +vfloat16m4_t test_vlmul_ext_v_f16mf4_f16m4(vfloat16mf4_t op1) {
> +  return __riscv_vlmul_ext_v_f16mf4_f16m4(op1);
> +}
> +
> +vfloat16m8_t test_vlmul_ext_v_f16mf2_f16m8(vfloat16mf2_t op1) {
> +  return __riscv_vlmul_ext_v_f16mf2_f16m8(op1);
> +}
> +
> +vfloat16m8_t test_vlmul_ext_v_f16mf4_f16m8(vfloat16mf4_t op1) {
> +  return __riscv_vlmul_ext_v_f16mf4_f16m8(op1);
> +}
> +
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 7 } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 12 } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m2,\s*t[au],\s*m[au]} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m4,\s*t[au],\s*m[au]} 1 } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 5 } } */
> /* { dg-final { scan-assembler-times
> {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> /* { dg-final { scan-assembler-times
> {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
> -/* { dg-final { scan-assembler-times
> {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 8 } } */
> -/* { dg-final { scan-assembler-times
> {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 7 } } */
> +/* { dg-final { scan-assembler-times
> {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> +/* { dg-final { scan-assembler-times
> {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 8 } } */
> +/* { dg-final { scan-assembler-times
> {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 2 } } */
> +/* { dg-final { scan-assembler-times
> {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 2 } } */
> /* { dg-final { scan-assembler-times
> {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> -/* { dg-final { scan-assembler-times
> {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */
> +/* { dg-final { scan-assembler-times
> {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 2 } } */
> +/* { dg-final { scan-assembler-times
> {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> +/* { dg-final { scan-assembler-times
> {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> +/* { dg-final { scan-assembler-times
> {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> +/* { dg-final { scan-assembler-times
> {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 11 } } */
> --
> 2.34.1
>
>
>