Re: [PATCH] RISC-V: Add missing vsetvl instruction type.

[Kito Cheng <kito.cheng@gmail.com>]

Committed, thanks :)

On Mon, Oct 10, 2022 at 9:44 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> When implementing built-in framework, I notice I missed
> vsetvl instruction type, so add it in a single patch
> preparing for the following patches.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.md: Add vsetvl instruction type.
>
> ---
>  gcc/config/riscv/riscv.md | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 014206fb8bd..2d1cda2b98f 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -229,6 +229,7 @@
>  ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
>  ;; rdvlenb     vector byte length vlenb csrr read
>  ;; rdvl        vector length vl csrr read
> +;; vsetvl      vector configuration-setting instrucions
>  ;; 7. Vector Loads and Stores
>  ;; vlde        vector unit-stride load instructions
>  ;; vste        vector unit-stride store instructions
> @@ -316,7 +317,7 @@
>    "unknown,branch,jump,call,load,fpload,store,fpstore,
>     mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
>     fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
> -   rdvlenb,rdvl,vlde,vste,vldm,vstm,vlds,vsts,
> +   rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
>     vldux,vldox,vstux,vstox,vldff,vldr,vstr,
>     vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,
>     vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,
> --
> 2.36.1
>