From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id B94F138362CE for ; Thu, 1 Sep 2022 02:05:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B94F138362CE Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x632.google.com with SMTP id gb36so10956128ejc.10 for ; Wed, 31 Aug 2022 19:05:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=kOcponb80UnxPztHNN2VJ8z5Ke1gISAH/AhcZ/kwuHE=; b=jMk273hxN/cGrUsRvTod7arAkrgGnXvvwobeLDdPVFe12evhLQDSdYcgFkpGod96iK e4EGo8qF0EsDehwZ1XyC5dyQ19vSxDLiK2XT8DRZQ6SooOiBkfBQ79/PZqJH0UAShoIN QCm4emwa/cuoQZMI/iEHhBJzJ8zcYa+RJDRMdY3ZV5sLsumOmm9wnAPz1TUu+YUf9nUS b6w2Z++GGbwHrsUemUyQfxfCnCQiodU54UsvQx02y5JY2O/DqSFJKObp5niH6CujsZeF Mv4uUZB4/hHmCWCGur69ll+HEFIoVBuN17/t36/hoYAHa8ZC+ALYBCqjowRV5cpIJV7F 8pVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=kOcponb80UnxPztHNN2VJ8z5Ke1gISAH/AhcZ/kwuHE=; b=tlTn/FMOZvfP9OTV2F2JVTU3t85gO9WEcgA1LjvjZYcyhWZ1LXkMOlcM7rszkIFnud pP5FxehKum/QKcclBz5LiBWyeDDQjb81iZQTNFpmwUeefuz+QyEoFSxlIyq37s+pYBzx 4ABitqdM5ATb/7WrNZ0euUZ3aEavTb/ptp5pahsO8blwdu7Kb4h9sxvv1IZtpchyFrt9 AZHavr/O910U9GZb7D5vNGICQnYCTB0IjM9aym2Ct7bMLRnxJXliE2m4YXIh4Th9K3oI bpoNMFqUN9nd3M7mKu6cbQQ4Jogyb0fCzK51GMXpL6eXZkRkMaZsvaom6UwHQ78GYQRt CKuQ== X-Gm-Message-State: ACgBeo3/w+QUvAv83h3lCs27Vl6Cj+U4VOtZOwpXt0367VW9ddIVwfHh HSlpAFaa8QpqIHgP0pD3T3dxlZY7EMvksWUFguU= X-Google-Smtp-Source: AA6agR5mrkK/Rs0AQFzKfC0/xvpFJmn7gSfVjiemPOPXALMHYf4n+Nnx2hDhgloh4SUm8fssxJvuHsEPiJ9tnt6gajc= X-Received: by 2002:a17:906:ee89:b0:73d:70c5:1a4e with SMTP id wt9-20020a170906ee8900b0073d70c51a4emr21198309ejb.683.1661997937288; Wed, 31 Aug 2022 19:05:37 -0700 (PDT) MIME-Version: 1.0 References: <20220830015024.17543-1-juzhe.zhong@rivai.ai> In-Reply-To: <20220830015024.17543-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Thu, 1 Sep 2022 10:05:25 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN To: juzhe.zhong@rivai.ai Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Thanks, pushed with a few minor style fixes. On Tue, Aug 30, 2022 at 9:51 AM wrote: > > From: zhongjuzhe > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_convert_vector_bits): Change configuration according to TARGET_MIN_VLEN. > * config/riscv/riscv.h (UNITS_PER_FP_REG): Fix annotation. > > --- > gcc/config/riscv/riscv.cc | 11 ++++++----- > gcc/config/riscv/riscv.h | 2 +- > 2 files changed, 7 insertions(+), 6 deletions(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 4d439e15392..ef606f33983 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5219,14 +5219,15 @@ riscv_init_machine_status (void) > static poly_uint16 > riscv_convert_vector_bits (void) > { > - /* The runtime invariant is only meaningful when vector is enabled. */ > + /* The runtime invariant is only meaningful when TARGET_VECTOR is enabled. */ > if (!TARGET_VECTOR) > return 0; > > - if (TARGET_VECTOR_ELEN_64 || TARGET_VECTOR_ELEN_FP_64) > + if (TARGET_MIN_VLEN > 32) > { > - /* When targetting Zve64* (ELEN = 64) extensions, we should use 64-bit > - chunk size. Runtime invariant: The single indeterminate represent the > + /* When targetting minimum VLEN > 32, we should use 64-bit chunk size. > + Otherwise we can not include sew = 64bits. > + Runtime invariant: The single indeterminate represent the > number of 64-bit chunks in a vector beyond minimum length of 64 bits. > Thus the number of bytes in a vector is 8 + 8 * x1 which is > riscv_vector_chunks * 8 = poly_int (8, 8). */ > @@ -5234,7 +5235,7 @@ riscv_convert_vector_bits (void) > } > else > { > - /* When targetting Zve32* (ELEN = 32) extensions, we should use 32-bit > + /* When targetting minimum VLEN = 32, we should use 32-bit > chunk size. Runtime invariant: The single indeterminate represent the > number of 32-bit chunks in a vector beyond minimum length of 32 bits. > Thus the number of bytes in a vector is 4 + 4 * x1 which is > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 1d8139c2c9b..29582f7c545 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -160,7 +160,7 @@ ASM_MISA_SPEC > > /* The `Q' extension is not yet supported. */ > #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4) > -/* Size per vector register. For zve32*, size = poly (4, 4). Otherwise, size = poly (8, 8). */ > +/* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */ > #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk) > > /* The largest type that can be passed in floating-point registers. */ > -- > 2.36.1 >