From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id C9DF03858420 for ; Thu, 16 Nov 2023 07:34:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C9DF03858420 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C9DF03858420 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::631 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700120099; cv=none; b=Jmd8sgXtn7VguaDbY5TWZNe46xCoLkcjyOZnLXmzjCCRgBlnay9i//ft1lKCSP00P+RXB5VYG2WJ84HAEKS8tXkqkRVo9vVFsYx342g7YJ4SAzqq8C/k0/3FMVTyoKxVDGXhIk6VzaurYlgDUHYTqcDR380UmUiwp8Q/WJC+MwE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700120099; c=relaxed/simple; bh=eZyE3M6bbkWWRsvWJgpjNQigkda/d+GBuof6nmDDtzY=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=B6T+rtTsZYuM4huCYmF3hqK1jL1tGliHWmp9eS4G8+bnufGsNAk0gz7tqJsmm8Bvg2OhIdZ/b6ZvCWx9gcBjlEC9z9jAzfB++9r9tsjSGMjaYysOOMJJDjKLFdIOz66iDeMTUhuIO5sH3MPJCnr8uXKbOAmP7W9upX+VibbozNs= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-9f2a53704aaso60563966b.3 for ; Wed, 15 Nov 2023 23:34:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700120095; x=1700724895; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=ubBlRiWOaAVLDCNwDt64xaNf4LQOa065kgW6qMPk/PI=; b=aqGlJZxQD/0c50cn7sqPoaerGideZQjDBIPY/q5BwZF61OOr1PzS9BdylLpF26JWV3 9vVhjauOrhYXhhqa9quOCgvoPfviSZFyuBhHhn7V6jR02sAxqvkUfMibgfS31XPfa1tZ rjamtys9hUR6Mh876kc0SpMPE/i+Lbfj6PUOlne6ovrUoqRa8F2xk+V/Ty+RQ7vaYOLY 49LcwzVQ8XsWj5IOphiw+OcEThLPdefXRqN5Kl2Jw2U1QFIaJmwx+HB9CnJNQDlQAuVm zhoXX22udyPyxz0BUPA0vCqDGDOwHrTJ0rlVKZY0693tqDdLdzx/l2ZyvrqI1Ygt/5ac YaFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700120095; x=1700724895; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ubBlRiWOaAVLDCNwDt64xaNf4LQOa065kgW6qMPk/PI=; b=tWy2dBI8le8ys7DQYKrzkcbDVFfnB6tryuUGrpJFCgqDVzHhq3Lax25jsA2KKmwdxW 6p/f09GPSPziVqu6k9l7N0ULKj58yWEOYFTAZvn0/RhYu4I51jY+e80NzNkX6Ow15t66 JDuj02WGC9aTBSwdMZ0w+H2DXNxv8SqPvPe8JG/mcS4VxglZKph3dLKdnYvvmlYkXRU6 AkvriLQczX9Cqum0u14Z58r4+2z+6xmp61Ex5Ng2CSvlxw2uJSX9l2xb5MeZV2yFpsfL O7lQk6/DU9e7G0W3N/K91drb9N3VkqenUE8R/m/0IhXPlPtnAob8pGtyHSGbfVr1dzX+ ztDg== X-Gm-Message-State: AOJu0YzZcLKsPjU1Mf8z+xlSJ8P3iq680LoJWQuIrUz7/BN6p51OAaIE GiiWGfX7L/1vfZ6w6dpzfACFDd+qHXrA9mg+VPRqDa8PlkP0Uw== X-Google-Smtp-Source: AGHT+IE+jIqfa1eO3ml0CT4iKVdM+6zFIOmT/5mig8IvhELMmxr/wL33eXeozuDEaC+wWpiAlB3OTLZf8c3Hz3NOz/o= X-Received: by 2002:a17:906:fd1:b0:9be:6ccb:6a8f with SMTP id c17-20020a1709060fd100b009be6ccb6a8fmr10652240ejk.48.1700120095070; Wed, 15 Nov 2023 23:34:55 -0800 (PST) MIME-Version: 1.0 References: <20231115233042.557245-1-ewlu@rivosinc.com> In-Reply-To: <20231115233042.557245-1-ewlu@rivosinc.com> From: Kito Cheng Date: Thu, 16 Nov 2023 15:34:43 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557] To: Edwin Lu Cc: gcc-patches@gcc.gnu.org, gnu-toolchain@rivosinc.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: ohhh, thanks for fixing that, LGTM! On Thu, Nov 16, 2023 at 7:31=E2=80=AFAM Edwin Lu wrote: > > Fix __riscv_unaligned_fast/slow/avoid macro name to > __riscv_misaligned_fast/slow/avoid to be consistent with the RISC-V API S= pec > > gcc/ChangeLog: > > * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): update macro = name > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/attribute-1.c: update macro name > * gcc.target/riscv/attribute-4.c: ditto > * gcc.target/riscv/attribute-5.c: ditto > * gcc.target/riscv/predef-align-1.c: ditto > * gcc.target/riscv/predef-align-2.c: ditto > * gcc.target/riscv/predef-align-3.c: ditto > * gcc.target/riscv/predef-align-4.c: ditto > * gcc.target/riscv/predef-align-5.c: ditto > * gcc.target/riscv/predef-align-6.c: ditto > > Signed-off-by: Edwin Lu > --- > gcc/config/riscv/riscv-c.cc | 6 +++--- > gcc/testsuite/gcc.target/riscv/attribute-1.c | 10 +++++----- > gcc/testsuite/gcc.target/riscv/attribute-4.c | 8 ++++---- > gcc/testsuite/gcc.target/riscv/attribute-5.c | 10 +++++----- > gcc/testsuite/gcc.target/riscv/predef-align-1.c | 10 +++++----- > gcc/testsuite/gcc.target/riscv/predef-align-2.c | 8 ++++---- > gcc/testsuite/gcc.target/riscv/predef-align-3.c | 10 +++++----- > gcc/testsuite/gcc.target/riscv/predef-align-4.c | 10 +++++----- > gcc/testsuite/gcc.target/riscv/predef-align-5.c | 8 ++++---- > gcc/testsuite/gcc.target/riscv/predef-align-6.c | 10 +++++----- > 10 files changed, 45 insertions(+), 45 deletions(-) > > diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc > index b7f9ba204f7..dd1bd0596fc 100644 > --- a/gcc/config/riscv/riscv-c.cc > +++ b/gcc/config/riscv/riscv-c.cc > @@ -109,11 +109,11 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) > } > > if (riscv_user_wants_strict_align) > - builtin_define_with_int_value ("__riscv_unaligned_avoid", 1); > + builtin_define_with_int_value ("__riscv_misaligned_avoid", 1); > else if (riscv_slow_unaligned_access_p) > - builtin_define_with_int_value ("__riscv_unaligned_slow", 1); > + builtin_define_with_int_value ("__riscv_misaligned_slow", 1); > else > - builtin_define_with_int_value ("__riscv_unaligned_fast", 1); > + builtin_define_with_int_value ("__riscv_misaligned_fast", 1); > > if (TARGET_MIN_VLEN !=3D 0) > builtin_define_with_int_value ("__riscv_v_min_vlen", TARGET_MIN_VLEN= ); > diff --git a/gcc/testsuite/gcc.target/riscv/attribute-1.c b/gcc/testsuite= /gcc.target/riscv/attribute-1.c > index abfb0b498e0..a39efb3e6ff 100644 > --- a/gcc/testsuite/gcc.target/riscv/attribute-1.c > +++ b/gcc/testsuite/gcc.target/riscv/attribute-1.c > @@ -4,13 +4,13 @@ int foo() > { > > /* In absence of -m[no-]strict-align, default mcpu is currently > - set to rocket. rocket has slow_unaligned_access=3Dtrue. */ > -#if !defined(__riscv_unaligned_slow) > -#error "__riscv_unaligned_slow is not set" > + set to rocket. rocket has slow_misaligned_access=3Dtrue. */ > +#if !defined(__riscv_misaligned_slow) > +#error "__riscv_misaligned_slow is not set" > #endif > > -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) > -#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedl= y set" > +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast= ) > +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpecte= dly set" > #endif > > return 0; > diff --git a/gcc/testsuite/gcc.target/riscv/attribute-4.c b/gcc/testsuite= /gcc.target/riscv/attribute-4.c > index 545f87cb899..a5a95042a31 100644 > --- a/gcc/testsuite/gcc.target/riscv/attribute-4.c > +++ b/gcc/testsuite/gcc.target/riscv/attribute-4.c > @@ -3,12 +3,12 @@ > int foo() > { > > -#if !defined(__riscv_unaligned_avoid) > -#error "__riscv_unaligned_avoid is not set" > +#if !defined(__riscv_misaligned_avoid) > +#error "__riscv_misaligned_avoid is not set" > #endif > > -#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow) > -#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly= set" > +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) > +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpected= ly set" > #endif > > return 0; > diff --git a/gcc/testsuite/gcc.target/riscv/attribute-5.c b/gcc/testsuite= /gcc.target/riscv/attribute-5.c > index 753043c31e9..ad1a1811fa3 100644 > --- a/gcc/testsuite/gcc.target/riscv/attribute-5.c > +++ b/gcc/testsuite/gcc.target/riscv/attribute-5.c > @@ -3,13 +3,13 @@ > int foo() > { > > -/* Default mcpu is rocket which has slow_unaligned_access=3Dtrue. */ > -#if !defined(__riscv_unaligned_slow) > -#error "__riscv_unaligned_slow is not set" > +/* Default mcpu is rocket which has slow_misaligned_access=3Dtrue. */ > +#if !defined(__riscv_misaligned_slow) > +#error "__riscv_misaligned_slow is not set" > #endif > > -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) > -#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedl= y set" > +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast= ) > +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpecte= dly set" > #endif > > return 0; > diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-1.c b/gcc/testsu= ite/gcc.target/riscv/predef-align-1.c > index 9dde37a721e..fb8c5f74035 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-align-1.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-align-1.c > @@ -3,13 +3,13 @@ > > int main() { > > -/* thead-c906 default is cpu tune param unaligned access fast */ > -#if !defined(__riscv_unaligned_fast) > -#error "__riscv_unaligned_fast is not set" > +/* thead-c906 default is cpu tune param misaligned access fast */ > +#if !defined(__riscv_misaligned_fast) > +#error "__riscv_misaligned_fast is not set" > #endif > > -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_slow) > -#error "__riscv_unaligned_avoid or __riscv_unaligned_slow is unexpectedl= y set" > +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_slow= ) > +#error "__riscv_misaligned_avoid or __riscv_misaligned_slow is unexpecte= dly set" > #endif > > return 0; > diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-2.c b/gcc/testsu= ite/gcc.target/riscv/predef-align-2.c > index 33d604f5aa0..50ab67e04f5 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-align-2.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-align-2.c > @@ -3,12 +3,12 @@ > > int main() { > > -#if !defined(__riscv_unaligned_avoid) > -#error "__riscv_unaligned_avoid is not set" > +#if !defined(__riscv_misaligned_avoid) > +#error "__riscv_misaligned_avoid is not set" > #endif > > -#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow) > -#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly= set" > +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) > +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpected= ly set" > #endif > > return 0; > diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-3.c b/gcc/testsu= ite/gcc.target/riscv/predef-align-3.c > index daf5718a39f..5c586907cb0 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-align-3.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-align-3.c > @@ -3,13 +3,13 @@ > > int main() { > > -/* thead-c906 default is cpu tune param unaligned access fast */ > -#if !defined(__riscv_unaligned_fast) > -#error "__riscv_unaligned_fast is not set" > +/* thead-c906 default is cpu tune param misaligned access fast */ > +#if !defined(__riscv_misaligned_fast) > +#error "__riscv_misaligned_fast is not set" > #endif > > -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_slow) > -#error "__riscv_unaligned_avoid or __riscv_unaligned_slow is unexpectedl= y set" > +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_slow= ) > +#error "__riscv_misaligned_avoid or __riscv_misaligned_slow is unexpecte= dly set" > #endif > > return 0; > diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-4.c b/gcc/testsu= ite/gcc.target/riscv/predef-align-4.c > index d46a46f252d..6fbdc7f7d41 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-align-4.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-align-4.c > @@ -3,13 +3,13 @@ > > int main() { > > -/* rocket default is cpu tune param unaligned access slow */ > -#if !defined(__riscv_unaligned_slow) > -#error "__riscv_unaligned_slow is not set" > +/* rocket default is cpu tune param misaligned access slow */ > +#if !defined(__riscv_misaligned_slow) > +#error "__riscv_misaligned_slow is not set" > #endif > > -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) > -#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedl= y set" > +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast= ) > +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpecte= dly set" > #endif > > return 0; > diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-5.c b/gcc/testsu= ite/gcc.target/riscv/predef-align-5.c > index 3aa25f8e0e0..4a40081d86d 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-align-5.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-align-5.c > @@ -3,12 +3,12 @@ > > int main() { > > -#if !defined(__riscv_unaligned_avoid) > -#error "__riscv_unaligned_avoid is not set" > +#if !defined(__riscv_misaligned_avoid) > +#error "__riscv_misaligned_avoid is not set" > #endif > > -#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow) > -#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly= set" > +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) > +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpected= ly set" > #endif > > return 0; > diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-6.c b/gcc/testsu= ite/gcc.target/riscv/predef-align-6.c > index cb64d7e7778..18eb72cfc60 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-align-6.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-align-6.c > @@ -3,13 +3,13 @@ > > int main() { > > -/* rocket default is cpu tune param unaligned access slow */ > -#if !defined(__riscv_unaligned_slow) > -#error "__riscv_unaligned_slow is not set" > +/* rocket default is cpu tune param misaligned access slow */ > +#if !defined(__riscv_misaligned_slow) > +#error "__riscv_misaligned_slow is not set" > #endif > > -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) > -#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedl= y set" > +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast= ) > +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpecte= dly set" > #endif > > return 0; > -- > 2.34.1 >