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Sun, 02 Jun 2024 22:14:30 -0700 (PDT) MIME-Version: 1.0 References: <312de1e592b96ee2ccd10829c17cfb9df93b13da.1717134752.git.linkw@linux.ibm.com> In-Reply-To: <312de1e592b96ee2ccd10829c17cfb9df93b13da.1717134752.git.linkw@linux.ibm.com> From: Kito Cheng Date: Mon, 3 Jun 2024 13:14:19 +0800 Message-ID: Subject: Re: [PATCH 41/52] riscv: New hook implementation riscv_c_mode_for_floating_type To: Kewen Lin Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com, andrew@sifive.com, jim.wilson.gcc@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM from RISC-V, thanks :) On Mon, Jun 3, 2024 at 11:08=E2=80=AFAM Kewen Lin wro= te: > > This is to remove macros {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE > defines in riscv port, and add new port specific hook > implementation riscv_c_mode_for_floating_type. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_c_mode_for_floating_type): New fun= ction. > (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro. > * config/riscv/riscv.h (FLOAT_TYPE_SIZE): Remove. > (DOUBLE_TYPE_SIZE): Likewise. > (LONG_DOUBLE_TYPE_SIZE): Likewise. > --- > gcc/config/riscv/riscv.cc | 15 +++++++++++++++ > gcc/config/riscv/riscv.h | 4 ---- > 2 files changed, 15 insertions(+), 4 deletions(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 92935275aaa..b011344cabe 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -11449,6 +11449,18 @@ riscv_expand_usadd (rtx dest, rtx x, rtx y) > emit_move_insn (dest, gen_lowpart (mode, xmode_dest)); > } > > +/* Implement TARGET_C_MODE_FOR_FLOATING_TYPE. Return TFmode for > + TI_LONG_DOUBLE_TYPE which is for long double type, go with the > + default one for the others. */ > + > +static machine_mode > +riscv_c_mode_for_floating_type (enum tree_index ti) > +{ > + if (ti =3D=3D TI_LONG_DOUBLE_TYPE) > + return TFmode; > + return default_mode_for_floating_type (ti); > +} > + > /* Initialize the GCC target structure. */ > #undef TARGET_ASM_ALIGNED_HI_OP > #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" > @@ -11804,6 +11816,9 @@ riscv_expand_usadd (rtx dest, rtx x, rtx y) > #undef TARGET_GET_RAW_RESULT_MODE > #define TARGET_GET_RAW_RESULT_MODE riscv_get_raw_result_mode > > +#undef TARGET_C_MODE_FOR_FLOATING_TYPE > +#define TARGET_C_MODE_FOR_FLOATING_TYPE riscv_c_mode_for_floating_type > + > struct gcc_target targetm =3D TARGET_INITIALIZER; > > #include "gt-riscv.h" > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index d6b14c4d620..83c4677c6a1 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -188,10 +188,6 @@ ASM_MISA_SPEC > #define POINTER_SIZE (riscv_abi >=3D ABI_LP64 ? 64 : 32) > #define LONG_TYPE_SIZE POINTER_SIZE > > -#define FLOAT_TYPE_SIZE 32 > -#define DOUBLE_TYPE_SIZE 64 > -#define LONG_DOUBLE_TYPE_SIZE 128 > - > /* Allocation boundary (in *bits*) for storing arguments in argument lis= t. */ > #define PARM_BOUNDARY BITS_PER_WORD > > -- > 2.43.0 >