From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by sourceware.org (Postfix) with ESMTPS id 817B53858D35 for ; Thu, 4 Nov 2021 14:59:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 817B53858D35 Received: by mail-ed1-x52b.google.com with SMTP id c8so5731645ede.13 for ; Thu, 04 Nov 2021 07:59:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=SuyYHUGETDrzKuEw4oYXPvZQ5f3HIq9QpfxXTLO5QN0=; b=KZMkuF8YUCNxJpW+p9xTQnTrGxAbDuu08pWjWCClhKSnn3AMHBbZkyux4PhszuQOV9 yxMjWnHolM77xbQKnQy3GOeTHPLoD+Eq+ZHOUHHLRNBHd+1q/n2Sn0fxwdckUtPvVPK2 FUa0LOblbMqjBzGBnyTiVaq0Mk2sKZqtKqsMl9sCXqg37RTjG5vdHJMM8fUdOlnskENm GhEpcAwsZnPANA0vPHstTGavVpQtpZRzSQgaf+NE+GzT9TU9nOOfaLtMkEwnlk7f6DSM 83f0V4TT2nXsXv5Z3hikirYXusnPFa+SizdyaMPycAKlEVJHzroAKThNcruXLeyfvKlf bA1Q== X-Gm-Message-State: AOAM5318pM7EHSACufza9OIxpPXDO4XoxQ/gTyVbxqdbXgEpvDb7F4Xc lMv6FAezh+nVy8DrF1Jr5jEgPqQd9O3J8PeM0nw= X-Google-Smtp-Source: ABdhPJyJdDfG+H3aGGS/eLlPNM0t2uSmRUQOF8vhVg6iYZ/5wTKaaOoQBU9T/zU8NsU9rXRCMiAJLqBXAX+YeJg10bc= X-Received: by 2002:aa7:cdc9:: with SMTP id h9mr42117584edw.370.1636037967322; Thu, 04 Nov 2021 07:59:27 -0700 (PDT) MIME-Version: 1.0 References: <20211028135246.9699-1-jiawei@iscas.ac.cn> <20211028135246.9699-4-jiawei@iscas.ac.cn> In-Reply-To: <20211028135246.9699-4-jiawei@iscas.ac.cn> From: Kito Cheng Date: Thu, 4 Nov 2021 22:59:15 +0800 Message-ID: Subject: Re: [PATCH 3/3] RISC-V: Imply info and regs limit for zfinx extension To: jiawei Cc: GCC Patches , Christoph Muellner , Andrew Waterman , sinan , tariq.kurd=huawei.com@lists.riscv.org, Kito Cheng Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Nov 2021 14:59:32 -0000 On Thu, Oct 28, 2021 at 9:57 PM jiawei wrote: > > Co-Authored-By: sinan > --- > gcc/config/riscv/arch-canonicalize | 1 + > gcc/config/riscv/constraints.md | 3 ++- > gcc/config/riscv/riscv.c | 15 +++++++++++++-- > 3 files changed, 16 insertions(+), 3 deletions(-) > > diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize > index ea95a0693f3..3bb195416b4 100755 > --- a/gcc/config/riscv/arch-canonicalize > +++ b/gcc/config/riscv/arch-canonicalize > @@ -36,6 +36,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x'] > # > IMPLIED_EXT = { > "d" : ["f"], > + "zdinx" : ["zfinx"], > } > > def arch_canonicalize(arch): > diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md > index c87d5b796a5..a99b8ce277e 100644 > --- a/gcc/config/riscv/constraints.md > +++ b/gcc/config/riscv/constraints.md > @@ -20,8 +20,9 @@ > ;; . > > ;; Register constraints > +;; Zfinx support need refuse FPR and use GPR > > -(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" > +(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)" > "A floating-point register (if available).") > > (define_register_constraint "j" "SIBCALL_REGS" > diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c > index 6aef3d3a6cf..505435c3cee 100644 > --- a/gcc/config/riscv/riscv.c > +++ b/gcc/config/riscv/riscv.c > @@ -4013,7 +4013,7 @@ riscv_compute_frame_info (void) > > /* Find out which FPRs we need to save. This loop must iterate over > the same space as its companion in riscv_for_each_saved_reg. */ > - if (TARGET_HARD_FLOAT) > + if (TARGET_HARD_FLOAT && !TARGET_ZFINX) `F` and `ZFINX` should be incompatible so I think this check is not needed. > for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) > if (riscv_save_reg_p (regno)) > frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++; > @@ -4790,6 +4790,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) > != call_used_or_fixed_reg_p (regno + i)) > return false; > > + /* Only use even registers in RV32 ZFINX */ RV32 ZDINX? > + if (!TARGET_64BIT && TARGET_ZDINX){ > + if (GET_MODE_CLASS (mode) == MODE_FLOAT && > + GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode)) > + return !(regno & 1); > + } > + > return true; > } > > @@ -4981,7 +4988,7 @@ riscv_option_override (void) > error ("%<-mdiv%> requires %<-march%> to subsume the % extension"); > > /* Likewise floating-point division and square root. */ > - if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) > + if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0) > target_flags |= MASK_FDIV; > > /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune > @@ -5027,6 +5034,10 @@ riscv_option_override (void) > if (TARGET_RVE && riscv_abi != ABI_ILP32E) > error ("rv32e requires ilp32e ABI"); > > + // Zfinx require abi ilp32,ilp32e or lp64. > + if (TARGET_ZFINX && riscv_abi != ABI_ILP32 && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E) This line is over 80 characters, you need to split this line into multiple line. > + error ("z*inx requires ABI ilp32, ilp32e or lp64"); > + > /* We do not yet support ILP32 on RV64. */ > if (BITS_PER_WORD != POINTER_SIZE) > error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); > -- > 2.25.1 >