[PATCH 0/3] RISC-V: Zfinx extension support

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* [PATCH 0/3] RISC-V: Zfinx extension support
@ 2021-10-28 13:52 jiawei
  2021-10-28 13:52 ` [PATCH 1/3] RISC-V: Minimal support of zfinx extension jiawei
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: jiawei @ 2021-10-28 13:52 UTC (permalink / raw)
  To: gcc-patches
  Cc: tariq.kurd=huawei.com, kito.cheng, jimw, jeremy.bennett,
	cmuellner, palmer, andrew, jiawei

Zfinx extension[1] had already finished public review. Here is the implementation patch set that reuse floating point pattern and ban the use of fpr when use zfinx as a target.

Current works can be find in follow links, we will keep update zhinx and zhinxmin after zfh extension goes upstream.
  https://github.com/pz9115/riscv-gcc/tree/zfinx-rebase
  https://github.com/pz9115/riscv-binutils-gdb/tree/zfinx-rebase

For test you can use qemu or spike that support zfinx extension, the
qemu will go upstream soon and spike is still in review:
  https://github.com/plctlab/plct-qemu/tree/plct-zfinx-dev
  https://github.com/plctlab/plct-spike/tree/plct-upstream-zfinx  

Thanks for Tariq Kurd, Kito Cheng, Jim Willson, Jeremy Bennett helped us a lot with this work.

[1] https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf

jiawei sinan (3):
  RISC-V: Minimal support of zfinx extension
  RISC-V: Target support for zfinx extension
  RISC-V: Imply info and regs limit for zfinx extension

 gcc/common/config/riscv/riscv-common.c |  6 +++
 gcc/config/riscv/arch-canonicalize     |  1 +
 gcc/config/riscv/constraints.md        |  3 +-
 gcc/config/riscv/riscv-builtins.c      |  4 +-
 gcc/config/riscv/riscv-c.c             |  2 +-
 gcc/config/riscv/riscv-opts.h          |  6 +++
 gcc/config/riscv/riscv.c               | 15 +++++-
 gcc/config/riscv/riscv.md              | 72 +++++++++++++-------------
 gcc/config/riscv/riscv.opt             |  3 ++
 9 files changed, 70 insertions(+), 42 deletions(-)


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 1/3] RISC-V: Minimal support of zfinx extension
  2021-10-28 13:52 [PATCH 0/3] RISC-V: Zfinx extension support jiawei
@ 2021-10-28 13:52 ` jiawei
  2021-11-04 15:04   ` Kito Cheng
  2021-10-28 13:52 ` [PATCH 2/3] RISC-V: Target support for " jiawei
  2021-10-28 13:52 ` [PATCH 3/3] RISC-V: Imply info and regs limit " jiawei
  2 siblings, 1 reply; 6+ messages in thread
From: jiawei @ 2021-10-28 13:52 UTC (permalink / raw)
  To: gcc-patches
  Cc: tariq.kurd=huawei.com, kito.cheng, jimw, jeremy.bennett,
	cmuellner, palmer, andrew, jiawei, sinan

Co-Authored-By: sinan <sinan@isrc.iscas.ac.cn>
---
 gcc/common/config/riscv/riscv-common.c | 6 ++++++
 gcc/config/riscv/riscv-opts.h          | 6 ++++++
 gcc/config/riscv/riscv.opt             | 3 +++
 3 files changed, 15 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 37b6ea80086..ab48909e338 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -106,6 +106,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -916,6 +919,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zbc",    &gcc_options::x_riscv_zb_subext, MASK_ZBC},
   {"zbs",    &gcc_options::x_riscv_zb_subext, MASK_ZBS},
 
+  {"zfinx",    &gcc_options::x_riscv_zf_subext, MASK_ZFINX},
+  {"zdinx",    &gcc_options::x_riscv_zf_subext, MASK_ZDINX},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 2efc4b80f1f..5a790a028cf 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -83,4 +83,10 @@ enum stack_protector_guard {
 #define TARGET_ZBC    ((riscv_zb_subext & MASK_ZBC) != 0)
 #define TARGET_ZBS    ((riscv_zb_subext & MASK_ZBS) != 0)
 
+#define MASK_ZFINX      (1 << 0)
+#define MASK_ZDINX      (1 << 1)
+
+#define TARGET_ZFINX    ((riscv_zf_subext & MASK_ZFINX) != 0)
+#define TARGET_ZDINX    ((riscv_zf_subext & MASK_ZDINX) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 15bf89e17c2..54d27747eff 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -198,6 +198,9 @@ int riscv_zi_subext
 TargetVariable
 int riscv_zb_subext
 
+TargetVariable
+int riscv_zf_subext
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
-- 
2.25.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/3] RISC-V: Minimal support of zfinx extension
  2021-10-28 13:52 ` [PATCH 1/3] RISC-V: Minimal support of zfinx extension jiawei
@ 2021-11-04 15:04   ` Kito Cheng
  0 siblings, 0 replies; 6+ messages in thread
From: Kito Cheng @ 2021-11-04 15:04 UTC (permalink / raw)
  To: jiawei
  Cc: GCC Patches, Christoph Muellner, Andrew Waterman, sinan,
	tariq.kurd=huawei.com, Kito Cheng

Could you add the information about zdinx implied zfinx to riscv_implied_info_t?

Thanks!

On Thu, Oct 28, 2021 at 9:56 PM jiawei <jiawei@iscas.ac.cn> wrote:
>
> Co-Authored-By: sinan <sinan@isrc.iscas.ac.cn>
> ---
>  gcc/common/config/riscv/riscv-common.c | 6 ++++++
>  gcc/config/riscv/riscv-opts.h          | 6 ++++++
>  gcc/config/riscv/riscv.opt             | 3 +++
>  3 files changed, 15 insertions(+)
>
> diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
> index 37b6ea80086..ab48909e338 100644
> --- a/gcc/common/config/riscv/riscv-common.c
> +++ b/gcc/common/config/riscv/riscv-common.c
> @@ -106,6 +106,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
>
> +  {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0},
> +
>    /* Terminate the list.  */
>    {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
>  };
> @@ -916,6 +919,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"zbc",    &gcc_options::x_riscv_zb_subext, MASK_ZBC},
>    {"zbs",    &gcc_options::x_riscv_zb_subext, MASK_ZBS},
>
> +  {"zfinx",    &gcc_options::x_riscv_zf_subext, MASK_ZFINX},
> +  {"zdinx",    &gcc_options::x_riscv_zf_subext, MASK_ZDINX},
> +
>    {NULL, NULL, 0}
>  };
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 2efc4b80f1f..5a790a028cf 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -83,4 +83,10 @@ enum stack_protector_guard {
>  #define TARGET_ZBC    ((riscv_zb_subext & MASK_ZBC) != 0)
>  #define TARGET_ZBS    ((riscv_zb_subext & MASK_ZBS) != 0)
>
> +#define MASK_ZFINX      (1 << 0)
> +#define MASK_ZDINX      (1 << 1)
> +
> +#define TARGET_ZFINX    ((riscv_zf_subext & MASK_ZFINX) != 0)
> +#define TARGET_ZDINX    ((riscv_zf_subext & MASK_ZDINX) != 0)
> +
>  #endif /* ! GCC_RISCV_OPTS_H */
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 15bf89e17c2..54d27747eff 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -198,6 +198,9 @@ int riscv_zi_subext
>  TargetVariable
>  int riscv_zb_subext
>
> +TargetVariable
> +int riscv_zf_subext
> +
>  Enum
>  Name(isa_spec_class) Type(enum riscv_isa_spec_class)
>  Supported ISA specs (for use with the -misa-spec= option):
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 2/3] RISC-V: Target support  for zfinx extension
  2021-10-28 13:52 [PATCH 0/3] RISC-V: Zfinx extension support jiawei
  2021-10-28 13:52 ` [PATCH 1/3] RISC-V: Minimal support of zfinx extension jiawei
@ 2021-10-28 13:52 ` jiawei
  2021-10-28 13:52 ` [PATCH 3/3] RISC-V: Imply info and regs limit " jiawei
  2 siblings, 0 replies; 6+ messages in thread
From: jiawei @ 2021-10-28 13:52 UTC (permalink / raw)
  To: gcc-patches
  Cc: tariq.kurd=huawei.com, kito.cheng, jimw, jeremy.bennett,
	cmuellner, palmer, andrew, jiawei, sinan

Co-Authored-By: sinan <sinan@isrc.iscas.ac.cn>
---
 gcc/config/riscv/riscv-builtins.c |  4 +-
 gcc/config/riscv/riscv-c.c        |  2 +-
 gcc/config/riscv/riscv.md         | 72 +++++++++++++++----------------
 3 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c
index 97b1480a15e..d892e6cdb26 100644
--- a/gcc/config/riscv/riscv-builtins.c
+++ b/gcc/config/riscv/riscv-builtins.c
@@ -85,7 +85,7 @@ struct riscv_builtin_description {
   unsigned int (*avail) (void);
 };
 
-AVAIL (hard_float, TARGET_HARD_FLOAT)
+AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -279,7 +279,7 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
 void
 riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
 {
-  if (!TARGET_HARD_FLOAT)
+  if (!(TARGET_HARD_FLOAT || TARGET_ZFINX))
     return;
 
   tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags);
diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
index efd4a61ea29..d064a7fc2b3 100644
--- a/gcc/config/riscv/riscv-c.c
+++ b/gcc/config/riscv/riscv-c.c
@@ -58,7 +58,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   if (TARGET_HARD_FLOAT)
     builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
 
-  if (TARGET_HARD_FLOAT && TARGET_FDIV)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV)
     {
       builtin_define ("__riscv_fdiv");
       builtin_define ("__riscv_fsqrt");
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index dd4c24292f2..0fef80c8742 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -296,8 +296,8 @@
 (define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
 
 ;; Iterator for hardware-supported floating-point modes.
-(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
-			    (DF "TARGET_DOUBLE_FLOAT")])
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
+			    (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")])
 
 ;; Iterator for floating-point modes that can be loaded into X registers.
 (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT")])
@@ -444,7 +444,7 @@
   [(set (match_operand:ANYF            0 "register_operand" "=f")
 	(plus:ANYF (match_operand:ANYF 1 "register_operand" " f")
 		   (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fadd.<fmt>\t%0,%1,%2"
   [(set_attr "type" "fadd")
    (set_attr "mode" "<UNITMODE>")])
@@ -575,7 +575,7 @@
   [(set (match_operand:ANYF             0 "register_operand" "=f")
 	(minus:ANYF (match_operand:ANYF 1 "register_operand" " f")
 		    (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fsub.<fmt>\t%0,%1,%2"
   [(set_attr "type" "fadd")
    (set_attr "mode" "<UNITMODE>")])
@@ -745,7 +745,7 @@
   [(set (match_operand:ANYF               0 "register_operand" "=f")
 	(mult:ANYF (match_operand:ANYF    1 "register_operand" " f")
 		      (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fmul.<fmt>\t%0,%1,%2"
   [(set_attr "type" "fmul")
    (set_attr "mode" "<UNITMODE>")])
@@ -1052,7 +1052,7 @@
   [(set (match_operand:ANYF           0 "register_operand" "=f")
 	(div:ANYF (match_operand:ANYF 1 "register_operand" " f")
 		  (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT && TARGET_FDIV"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
   "fdiv.<fmt>\t%0,%1,%2"
   [(set_attr "type" "fdiv")
    (set_attr "mode" "<UNITMODE>")])
@@ -1067,7 +1067,7 @@
 (define_insn "sqrt<mode>2"
   [(set (match_operand:ANYF            0 "register_operand" "=f")
 	(sqrt:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT && TARGET_FDIV"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
 {
     return "fsqrt.<fmt>\t%0,%1";
 }
@@ -1082,7 +1082,7 @@
 	(fma:ANYF (match_operand:ANYF 1 "register_operand" " f")
 		  (match_operand:ANYF 2 "register_operand" " f")
 		  (match_operand:ANYF 3 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fmadd.<fmt>\t%0,%1,%2,%3"
   [(set_attr "type" "fmadd")
    (set_attr "mode" "<UNITMODE>")])
@@ -1093,7 +1093,7 @@
 	(fma:ANYF (match_operand:ANYF           1 "register_operand" " f")
 		  (match_operand:ANYF           2 "register_operand" " f")
 		  (neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fmsub.<fmt>\t%0,%1,%2,%3"
   [(set_attr "type" "fmadd")
    (set_attr "mode" "<UNITMODE>")])
@@ -1105,7 +1105,7 @@
 	    (neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
 	    (match_operand:ANYF           2 "register_operand" " f")
 	    (neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fnmadd.<fmt>\t%0,%1,%2,%3"
   [(set_attr "type" "fmadd")
    (set_attr "mode" "<UNITMODE>")])
@@ -1117,7 +1117,7 @@
 	    (neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
 	    (match_operand:ANYF           2 "register_operand" " f")
 	    (match_operand:ANYF           3 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fnmsub.<fmt>\t%0,%1,%2,%3"
   [(set_attr "type" "fmadd")
    (set_attr "mode" "<UNITMODE>")])
@@ -1130,7 +1130,7 @@
 		(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
 		(match_operand:ANYF           2 "register_operand" " f")
 		(neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))]
-  "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
   "fmadd.<fmt>\t%0,%1,%2,%3"
   [(set_attr "type" "fmadd")
    (set_attr "mode" "<UNITMODE>")])
@@ -1143,7 +1143,7 @@
 		(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
 		(match_operand:ANYF           2 "register_operand" " f")
 		(match_operand:ANYF           3 "register_operand" " f"))))]
-  "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
   "fmsub.<fmt>\t%0,%1,%2,%3"
   [(set_attr "type" "fmadd")
    (set_attr "mode" "<UNITMODE>")])
@@ -1156,7 +1156,7 @@
 		(match_operand:ANYF 1 "register_operand" " f")
 		(match_operand:ANYF 2 "register_operand" " f")
 		(match_operand:ANYF 3 "register_operand" " f"))))]
-  "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
   "fnmadd.<fmt>\t%0,%1,%2,%3"
   [(set_attr "type" "fmadd")
    (set_attr "mode" "<UNITMODE>")])
@@ -1169,7 +1169,7 @@
 		(match_operand:ANYF           1 "register_operand" " f")
 		(match_operand:ANYF           2 "register_operand" " f")
 		(neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))]
-  "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)"
   "fnmsub.<fmt>\t%0,%1,%2,%3"
   [(set_attr "type" "fmadd")
    (set_attr "mode" "<UNITMODE>")])
@@ -1184,7 +1184,7 @@
 (define_insn "abs<mode>2"
   [(set (match_operand:ANYF           0 "register_operand" "=f")
 	(abs:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fabs.<fmt>\t%0,%1"
   [(set_attr "type" "fmove")
    (set_attr "mode" "<UNITMODE>")])
@@ -1194,7 +1194,7 @@
 	(unspec:ANYF [(match_operand:ANYF 1 "register_operand" " f")
 		      (match_operand:ANYF 2 "register_operand" " f")]
 		     UNSPEC_COPYSIGN))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fsgnj.<fmt>\t%0,%1,%2"
   [(set_attr "type" "fmove")
    (set_attr "mode" "<UNITMODE>")])
@@ -1202,7 +1202,7 @@
 (define_insn "neg<mode>2"
   [(set (match_operand:ANYF           0 "register_operand" "=f")
 	(neg:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fneg.<fmt>\t%0,%1"
   [(set_attr "type" "fmove")
    (set_attr "mode" "<UNITMODE>")])
@@ -1218,7 +1218,7 @@
   [(set (match_operand:ANYF            0 "register_operand" "=f")
 	(smin:ANYF (match_operand:ANYF 1 "register_operand" " f")
 		   (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fmin.<fmt>\t%0,%1,%2"
   [(set_attr "type" "fmove")
    (set_attr "mode" "<UNITMODE>")])
@@ -1227,7 +1227,7 @@
   [(set (match_operand:ANYF            0 "register_operand" "=f")
 	(smax:ANYF (match_operand:ANYF 1 "register_operand" " f")
 		   (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fmax.<fmt>\t%0,%1,%2"
   [(set_attr "type" "fmove")
    (set_attr "mode" "<UNITMODE>")])
@@ -1288,7 +1288,7 @@
   [(set (match_operand:SF     0 "register_operand" "=f")
 	(float_truncate:SF
 	    (match_operand:DF 1 "register_operand" " f")))]
-  "TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT || TARGET_ZDINX"
   "fcvt.s.d\t%0,%1"
   [(set_attr "type" "fcvt")
    (set_attr "mode" "SF")])
@@ -1414,7 +1414,7 @@
   [(set (match_operand:DF     0 "register_operand" "=f")
 	(float_extend:DF
 	    (match_operand:SF 1 "register_operand" " f")))]
-  "TARGET_DOUBLE_FLOAT"
+  "TARGET_DOUBLE_FLOAT || TARGET_ZDINX"
   "fcvt.d.s\t%0,%1"
   [(set_attr "type" "fcvt")
    (set_attr "mode" "DF")])
@@ -1430,7 +1430,7 @@
   [(set (match_operand:GPR      0 "register_operand" "=r")
 	(fix:GPR
 	    (match_operand:ANYF 1 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,rtz"
   [(set_attr "type" "fcvt")
    (set_attr "mode" "<ANYF:MODE>")])
@@ -1439,7 +1439,7 @@
   [(set (match_operand:GPR      0 "register_operand" "=r")
 	(unsigned_fix:GPR
 	    (match_operand:ANYF 1 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fcvt.<GPR:ifmt>u.<ANYF:fmt> %0,%1,rtz"
   [(set_attr "type" "fcvt")
    (set_attr "mode" "<ANYF:MODE>")])
@@ -1448,7 +1448,7 @@
   [(set (match_operand:ANYF    0 "register_operand" "= f")
 	(float:ANYF
 	    (match_operand:GPR 1 "reg_or_0_operand" " rJ")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fcvt.<ANYF:fmt>.<GPR:ifmt>\t%0,%z1"
   [(set_attr "type" "fcvt")
    (set_attr "mode" "<ANYF:MODE>")])
@@ -1457,7 +1457,7 @@
   [(set (match_operand:ANYF    0 "register_operand" "= f")
 	(unsigned_float:ANYF
 	    (match_operand:GPR 1 "reg_or_0_operand" " rJ")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fcvt.<ANYF:fmt>.<GPR:ifmt>u\t%0,%z1"
   [(set_attr "type" "fcvt")
    (set_attr "mode" "<ANYF:MODE>")])
@@ -1467,7 +1467,7 @@
 	(unspec:GPR
 	    [(match_operand:ANYF 1 "register_operand" " f")]
 	    RINT))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,<rint_rm>"
   [(set_attr "type" "fcvt")
    (set_attr "mode" "<ANYF:MODE>")])
@@ -1741,7 +1741,7 @@
 (define_insn "*movdf_hardfloat_rv32"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,  *r,*r,*m")
 	(match_operand:DF 1 "move_operand"         " f,G,m,f,G,*r*G,*m,*r"))]
-  "!TARGET_64BIT && TARGET_DOUBLE_FLOAT
+  "!TARGET_64BIT && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX)
    && (register_operand (operands[0], DFmode)
        || reg_or_0_operand (operands[1], DFmode))"
   { return riscv_output_move (operands[0], operands[1]); }
@@ -2190,7 +2190,7 @@
 			(match_operand:ANYF 2 "register_operand")])
 		      (label_ref (match_operand 3 ""))
 		      (pc)))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
 {
   riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]),
 				   operands[1], operands[2]);
@@ -2279,7 +2279,7 @@
 	(match_operator:SI 1 "fp_scc_comparison"
 	     [(match_operand:ANYF 2 "register_operand")
 	      (match_operand:ANYF 3 "register_operand")]))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
 {
   riscv_expand_float_scc (operands[0], GET_CODE (operands[1]), operands[2],
 			  operands[3]);
@@ -2291,7 +2291,7 @@
 	 (match_operator:X 1 "fp_native_comparison"
 	     [(match_operand:ANYF 2 "register_operand" " f")
 	      (match_operand:ANYF 3 "register_operand" " f")]))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "f%C1.<fmt>\t%0,%2,%3"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "<UNITMODE>")])
@@ -2303,7 +2303,7 @@
 		      (match_operand:ANYF 2 "register_operand")]
 		     QUIET_COMPARISON))
 	       (clobber (match_scratch:X 3))])]
-  "TARGET_HARD_FLOAT")
+  "TARGET_HARD_FLOAT || TARGET_ZFINX")
 
 (define_insn "*f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_default"
    [(set (match_operand:X      0 "register_operand" "=r")
@@ -2312,7 +2312,7 @@
 	   (match_operand:ANYF 2 "register_operand" " f")]
 	  QUIET_COMPARISON))
     (clobber (match_scratch:X 3 "=&r"))]
-  "TARGET_HARD_FLOAT && ! HONOR_SNANS (<ANYF:MODE>mode)"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ! HONOR_SNANS (<ANYF:MODE>mode)"
   "frflags\t%3\n\tf<quiet_pattern>.<fmt>\t%0,%1,%2\n\tfsflags %3"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "<UNITMODE>")
@@ -2325,7 +2325,7 @@
 	   (match_operand:ANYF 2 "register_operand" " f")]
 	  QUIET_COMPARISON))
     (clobber (match_scratch:X 3 "=&r"))]
-  "TARGET_HARD_FLOAT && HONOR_SNANS (<ANYF:MODE>mode)"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && HONOR_SNANS (<ANYF:MODE>mode)"
   "frflags\t%3\n\tf<quiet_pattern>.<fmt>\t%0,%1,%2\n\tfsflags %3\n\tfeq.<fmt>\tzero,%1,%2"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "<UNITMODE>")
@@ -2729,12 +2729,12 @@
 (define_insn "riscv_frflags"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(unspec_volatile [(const_int 0)] UNSPECV_FRFLAGS))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "frflags\t%0")
 
 (define_insn "riscv_fsflags"
   [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSFLAGS)]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fsflags\t%0")
 
 (define_insn "riscv_mret"
-- 
2.25.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 3/3] RISC-V: Imply info and regs limit for zfinx extension
  2021-10-28 13:52 [PATCH 0/3] RISC-V: Zfinx extension support jiawei
  2021-10-28 13:52 ` [PATCH 1/3] RISC-V: Minimal support of zfinx extension jiawei
  2021-10-28 13:52 ` [PATCH 2/3] RISC-V: Target support for " jiawei
@ 2021-10-28 13:52 ` jiawei
  2021-11-04 14:59   ` Kito Cheng
  2 siblings, 1 reply; 6+ messages in thread
From: jiawei @ 2021-10-28 13:52 UTC (permalink / raw)
  To: gcc-patches
  Cc: tariq.kurd=huawei.com, kito.cheng, jimw, jeremy.bennett,
	cmuellner, palmer, andrew, jiawei, sinan

Co-Authored-By: sinan <sinan@isrc.iscas.ac.cn>
---
 gcc/config/riscv/arch-canonicalize |  1 +
 gcc/config/riscv/constraints.md    |  3 ++-
 gcc/config/riscv/riscv.c           | 15 +++++++++++++--
 3 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
index ea95a0693f3..3bb195416b4 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -36,6 +36,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 #
 IMPLIED_EXT = {
   "d" : ["f"],
+  "zdinx" : ["zfinx"],
 }
 
 def arch_canonicalize(arch):
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index c87d5b796a5..a99b8ce277e 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -20,8 +20,9 @@
 ;; <http://www.gnu.org/licenses/>.
 
 ;; Register constraints
+;; Zfinx support need refuse FPR and use GPR
 
-(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)"
   "A floating-point register (if available).")
 
 (define_register_constraint "j" "SIBCALL_REGS"
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 6aef3d3a6cf..505435c3cee 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -4013,7 +4013,7 @@ riscv_compute_frame_info (void)
 
       /* Find out which FPRs we need to save.  This loop must iterate over
 	 the same space as its companion in riscv_for_each_saved_reg.  */
-      if (TARGET_HARD_FLOAT)
+      if (TARGET_HARD_FLOAT && !TARGET_ZFINX)
 	for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
 	  if (riscv_save_reg_p (regno))
 	    frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++;
@@ -4790,6 +4790,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
 	!= call_used_or_fixed_reg_p (regno + i))
       return false;
 
+  /* Only use even registers in RV32 ZFINX */
+  if (!TARGET_64BIT && TARGET_ZDINX){
+    if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
+	GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
+      return !(regno & 1);
+  }
+
   return true;
 }
 
@@ -4981,7 +4988,7 @@ riscv_option_override (void)
     error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
 
   /* Likewise floating-point division and square root.  */
-  if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0)
     target_flags |= MASK_FDIV;
 
   /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
@@ -5027,6 +5034,10 @@ riscv_option_override (void)
   if (TARGET_RVE && riscv_abi != ABI_ILP32E)
     error ("rv32e requires ilp32e ABI");
 
+  // Zfinx require abi ilp32,ilp32e or lp64.
+  if (TARGET_ZFINX && riscv_abi != ABI_ILP32 && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
+  error ("z*inx requires ABI ilp32, ilp32e or lp64");
+
   /* We do not yet support ILP32 on RV64.  */
   if (BITS_PER_WORD != POINTER_SIZE)
     error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
-- 
2.25.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 3/3] RISC-V: Imply info and regs limit for zfinx extension
  2021-10-28 13:52 ` [PATCH 3/3] RISC-V: Imply info and regs limit " jiawei
@ 2021-11-04 14:59   ` Kito Cheng
  0 siblings, 0 replies; 6+ messages in thread
From: Kito Cheng @ 2021-11-04 14:59 UTC (permalink / raw)
  To: jiawei
  Cc: GCC Patches, Christoph Muellner, Andrew Waterman, sinan,
	tariq.kurd=huawei.com, Kito Cheng

On Thu, Oct 28, 2021 at 9:57 PM jiawei <jiawei@iscas.ac.cn> wrote:
>
> Co-Authored-By: sinan <sinan@isrc.iscas.ac.cn>
> ---
>  gcc/config/riscv/arch-canonicalize |  1 +
>  gcc/config/riscv/constraints.md    |  3 ++-
>  gcc/config/riscv/riscv.c           | 15 +++++++++++++--
>  3 files changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize
> index ea95a0693f3..3bb195416b4 100755
> --- a/gcc/config/riscv/arch-canonicalize
> +++ b/gcc/config/riscv/arch-canonicalize
> @@ -36,6 +36,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
>  #
>  IMPLIED_EXT = {
>    "d" : ["f"],
> +  "zdinx" : ["zfinx"],
>  }
>
>  def arch_canonicalize(arch):
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index c87d5b796a5..a99b8ce277e 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -20,8 +20,9 @@
>  ;; <http://www.gnu.org/licenses/>.
>
>  ;; Register constraints
> +;; Zfinx support need refuse FPR and use GPR
>
> -(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
> +(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)"
>    "A floating-point register (if available).")
>
>  (define_register_constraint "j" "SIBCALL_REGS"
> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
> index 6aef3d3a6cf..505435c3cee 100644
> --- a/gcc/config/riscv/riscv.c
> +++ b/gcc/config/riscv/riscv.c
> @@ -4013,7 +4013,7 @@ riscv_compute_frame_info (void)
>
>        /* Find out which FPRs we need to save.  This loop must iterate over
>          the same space as its companion in riscv_for_each_saved_reg.  */
> -      if (TARGET_HARD_FLOAT)
> +      if (TARGET_HARD_FLOAT && !TARGET_ZFINX)

`F` and `ZFINX` should be incompatible so I think this check is not needed.

>         for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
>           if (riscv_save_reg_p (regno))
>             frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++;
> @@ -4790,6 +4790,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
>         != call_used_or_fixed_reg_p (regno + i))
>        return false;
>
> +  /* Only use even registers in RV32 ZFINX */

RV32 ZDINX?

> +  if (!TARGET_64BIT && TARGET_ZDINX){
> +    if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
> +       GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
> +      return !(regno & 1);
> +  }
> +
>    return true;
>  }
>
> @@ -4981,7 +4988,7 @@ riscv_option_override (void)
>      error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
>
>    /* Likewise floating-point division and square root.  */
> -  if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
> +  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0)
>      target_flags |= MASK_FDIV;
>
>    /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
> @@ -5027,6 +5034,10 @@ riscv_option_override (void)
>    if (TARGET_RVE && riscv_abi != ABI_ILP32E)
>      error ("rv32e requires ilp32e ABI");
>
> +  // Zfinx require abi ilp32,ilp32e or lp64.
> +  if (TARGET_ZFINX && riscv_abi != ABI_ILP32 && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)

This line is over  80 characters, you need to split this line into
multiple line.

> +  error ("z*inx requires ABI ilp32, ilp32e or lp64");
> +
>    /* We do not yet support ILP32 on RV64.  */
>    if (BITS_PER_WORD != POINTER_SIZE)
>      error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2021-11-04 15:04 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-28 13:52 [PATCH 0/3] RISC-V: Zfinx extension support jiawei
2021-10-28 13:52 ` [PATCH 1/3] RISC-V: Minimal support of zfinx extension jiawei
2021-11-04 15:04   ` Kito Cheng
2021-10-28 13:52 ` [PATCH 2/3] RISC-V: Target support for " jiawei
2021-10-28 13:52 ` [PATCH 3/3] RISC-V: Imply info and regs limit " jiawei
2021-11-04 14:59   ` Kito Cheng

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