From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x936.google.com (mail-ua1-x936.google.com [IPv6:2607:f8b0:4864:20::936]) by sourceware.org (Postfix) with ESMTPS id 889B23858407 for ; Fri, 3 Feb 2023 07:16:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 889B23858407 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x936.google.com with SMTP id p14so328074uaa.8 for ; Thu, 02 Feb 2023 23:16:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=z2bO66jgCOtabom5aK9GDyWdjYAboT4Ty3YNdWdRyTQ=; b=VTrsrdtM3He5zRxJhm/80il+HOPkhlOeMaqP2Zzd13dBNkFdTuXGEnu9mTybX9XQOy 6pvs7qXIf+U9/IuOxiZO0etn27NkULKqufLB6XlH/cn/W4P8nIZUqt2rtE0Cty3a9f02 lLmuR0chWpzyNIi+fp39qOnBPorONFYQKOTdDbapaNtovcm/KqHJ6fqYJI0o0S6B/7uQ uhUycpctVpX/Ts5arwZrMnGLwfUQ+qOvZX5+FK+b9+E4N2DL+41nOLgx2W6KYdsxwfl0 bS9d0R9LA9spm1mYzjXZDUUZbTcOCM1a1Le6T4uOhNUCdQEnlFfcG1mUjIzkzke2BjJP PNlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=z2bO66jgCOtabom5aK9GDyWdjYAboT4Ty3YNdWdRyTQ=; b=oN3qZACfLy+QZTvgR22j1616+EsLNej75MccMAEnClKZUsvNNeMsmEyqkICivYd+/p CTIB8REwPOebawzRuZZj3wDCb0JsXWHX7hT3rkADxFNOvx6MoOi5ahbRvUAw07Kham5l UTylO7+VblweOHUIO0i1TouryjPFqMOO+oY1f6chsBEf8rH2/0o34OXuRQIAsizGW//d t4lP7/WFe4BEUfuubu88HTGuf6HkG/yulWKfTt394qkwf+2qUJMvWAadGqUWT79njhld 3t4W4t4zXCQH2DXDC6B1Nuqgkz3fjqefeg2ziCmwZZRg8j5OulyQSRTtD0MaDO1t9Fx1 6PYA== X-Gm-Message-State: AO0yUKWPu4y9aUSizorysWy5aQXUdk7ai3vdb09WDVqyF9nmAYO9xBKy kTbiUDhu80s7J0X0EmpnHzjmKy+28pXeXKp7dyo= X-Google-Smtp-Source: AK7set84Dllp1cIwiLXNcFdysuJo4SPtaPdL4r//hYtSDlx2LMZXPYnx96aNaWbMSfy4Hv9QTvQpGSr6kiGVnGTISxU= X-Received: by 2002:ab0:710a:0:b0:680:1bda:a0c8 with SMTP id x10-20020ab0710a000000b006801bdaa0c8mr243140uan.73.1675408561639; Thu, 02 Feb 2023 23:16:01 -0800 (PST) MIME-Version: 1.0 References: <20230203045851.43100-1-monk.chiang@sifive.com> In-Reply-To: <20230203045851.43100-1-monk.chiang@sifive.com> From: Kito Cheng Date: Fri, 3 Feb 2023 15:15:50 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Remove unnecessary register class. To: Monk Chiang , =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: committed, also updated mask for ALL_REGS, thanks. On Fri, Feb 3, 2023 at 12:59 PM Monk Chiang wrote: > > Avoid VL_REGS, VTYPE_REGS join register allocation. > > gcc/ChangeLog: > > * config/riscv/riscv.h: Remove VL_REGS, VTYPE_REGS class. > * config/riscv/riscv.cc: Ditto. > --- > gcc/config/riscv/riscv.cc | 8 +------- > gcc/config/riscv/riscv.h | 6 ------ > 2 files changed, 1 insertion(+), 13 deletions(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 209d9a53e7b..3b7804b7501 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -293,7 +293,7 @@ const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { > FP_REGS, FP_REGS, FP_REGS, FP_REGS, > FP_REGS, FP_REGS, FP_REGS, FP_REGS, > FP_REGS, FP_REGS, FP_REGS, FP_REGS, > - FRAME_REGS, FRAME_REGS, VL_REGS, VTYPE_REGS, > + FRAME_REGS, FRAME_REGS, NO_REGS, NO_REGS, > NO_REGS, NO_REGS, NO_REGS, NO_REGS, > NO_REGS, NO_REGS, NO_REGS, NO_REGS, > NO_REGS, NO_REGS, NO_REGS, NO_REGS, > @@ -5831,12 +5831,6 @@ riscv_class_max_nregs (reg_class_t rclass, machine_mode mode) > if (reg_class_subset_p (rclass, V_REGS)) > return riscv_hard_regno_nregs (V_REG_FIRST, mode); > > - if (reg_class_subset_p (rclass, VL_REGS)) > - return 1; > - > - if (reg_class_subset_p (rclass, VTYPE_REGS)) > - return 1; > - > return 0; > } > > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 0ab739bd6eb..02e1224c3cd 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -462,8 +462,6 @@ enum reg_class > GR_REGS, /* integer registers */ > FP_REGS, /* floating-point registers */ > FRAME_REGS, /* arg pointer and frame pointer */ > - VL_REGS, /* vl register */ > - VTYPE_REGS, /* vtype register */ > VM_REGS, /* v0.t registers */ > VD_REGS, /* vector registers except v0.t */ > V_REGS, /* vector registers */ > @@ -487,8 +485,6 @@ enum reg_class > "GR_REGS", \ > "FP_REGS", \ > "FRAME_REGS", \ > - "VL_REGS", \ > - "VTYPE_REGS", \ > "VM_REGS", \ > "VD_REGS", \ > "V_REGS", \ > @@ -514,8 +510,6 @@ enum reg_class > { 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \ > { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FP_REGS */ \ > { 0x00000000, 0x00000000, 0x00000003, 0x00000000 }, /* FRAME_REGS */ \ > - { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* VL_REGS */ \ > - { 0x00000000, 0x00000000, 0x00000008, 0x00000000 }, /* VTYPE_REGS */ \ > { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, /* V0_REGS */ \ > { 0x00000000, 0x00000000, 0x00000000, 0xfffffffe }, /* VNoV0_REGS */ \ > { 0x00000000, 0x00000000, 0x00000000, 0xffffffff }, /* V_REGS */ \ > -- > 2.37.2 >