From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x934.google.com (mail-ua1-x934.google.com [IPv6:2607:f8b0:4864:20::934]) by sourceware.org (Postfix) with ESMTPS id 97BE43858D32 for ; Tue, 14 Mar 2023 02:37:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 97BE43858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x934.google.com with SMTP id r7so5543254uaj.2 for ; Mon, 13 Mar 2023 19:37:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678761468; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=EvoRFVZWywiL66G9+ELggXxdL6bBxCrtDrN3jjNnE2w=; b=dynMbCIN6GEu/fyeWOuOWoOykD6mHnccFlrGzwbxZboEZw5AAZ9NQCotmSZKxucww0 B6doNiNHCCPccCGGyvL26rbNN/lYhcXBAv0HrN67pMccSEilz2PtYtDvQhd9/F2vN3wE bYXTmdopNoC+5N/YpPC4GpSUMP8mYvWbgGKHH0CDwhaxYaYFzHC8W/f0Nh2BfTQM2Gpk eeJKSjBXusgWhPAreqtm/zdshMz24WBSG73Z7VBZcLVbVf0JvuyQZINMIKVTen8lAJAl 1dMzHwQLNXf0nGosXUodYzePbzGaLEfHBIOYu6JhAoP+XdB2y3mNa0I/Jdvnxf69M5RA eJIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678761468; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EvoRFVZWywiL66G9+ELggXxdL6bBxCrtDrN3jjNnE2w=; b=v/eRKAZb8q0Wfwr4X0pAOw6wLes2f5GqYg23998XFJNd4exhJOy+r0qQJDjUbo6zZX N5tx7UXVZt0GLM1Eh1EEje01rjGM4goixbERQzvlhH7hkhj57sDpBxJuZWtEGE8T5exi GQnw/03fpWaEn8CJQldXET0sVudDPEls3v2NO7re3bkDHBM1Ws/UT8PP9ckz+o5fj+if SAtbUvTPch6U1KiN/gAqy6IbXdX3CgkTYpkp4PJvONJs+Fo4IM2nt8G8dkrsop6a75E5 FBuy8zOj3b2w41aX2HQ+SsoWQLyoOrw65UlETr3ejLI1nhjZ978pivJ+c8tFJ8ETk8ca CI9w== X-Gm-Message-State: AO0yUKXJmOjFo6+o6j3PTnRnkZCS/zs0ZIwZ197l9kJlUD/2kvBmux5E 5+k60g+ONwfVsqA1ymkfEadxiLO7f1DjgtsJL8c= X-Google-Smtp-Source: AK7set+0Ht9F4qt03QNPOA0JMhkzzeXe4HnmUC70okBZat0I2srjtTinDYqV7mX5IoQb1iNgeRpj0x7e7UdRLJByR4Q= X-Received: by 2002:ab0:4a1b:0:b0:68b:9eed:1c7c with SMTP id q27-20020ab04a1b000000b0068b9eed1c7cmr24608789uae.0.1678761467456; Mon, 13 Mar 2023 19:37:47 -0700 (PDT) MIME-Version: 1.0 References: <20230314022331.105558-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230314022331.105558-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Tue, 14 Mar 2023 10:37:36 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Fix bugs of ternary integer and floating-point ternary intrinsics. To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, kito-cheng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: IIRC the canonical form of (plus (op) (mult (op) (op))) is (plus (mult (op) (op) (op)), so using the first form might not friendly for the combine pass. On Tue, Mar 14, 2023 at 10:24=E2=80=AFAM wrote: > > From: Ju-Zhe Zhong > > Co-authored-by: kito-cheng > Co-authored-by: kito-cheng > > This patch is fixing the bugs reported by @kito. > > // vnmsub.vx vd, rs1, vs2, vm # vd[i] =3D -(x[rs1] * vd[i]) + vs2[i] > // vd =3D -(vb * a) + vc > // =3D -(3 * 1) + 10 > // =3D 7 > // GCC wrongly optmize this pattern to `3 - 10` due to we write wrong R= TL > // pattern. > // vd =3D (3 * 1) - 10 > // =3D 3 - 10 > // =3D -7 > // NOTE: GCC optimized (vb * a) - vc to vb - vc > > Signed-off-by: Ju-Zhe Zhong > Co-authored-by: kito-cheng > Co-authored-by: kito-cheng > > gcc/ChangeLog: > > * config/riscv/vector.md: Correct ternary patterns. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/bug-3.c: New test. > * gcc.target/riscv/rvv/base/bug-4.c: New test. > * gcc.target/riscv/rvv/base/bug-5.c: New test. > > --- > gcc/config/riscv/vector.md | 80 +++++++++---------- > .../gcc.target/riscv/rvv/base/bug-3.c | 22 +++++ > .../gcc.target/riscv/rvv/base/bug-4.c | 22 +++++ > .../gcc.target/riscv/rvv/base/bug-5.c | 22 +++++ > 4 files changed, 106 insertions(+), 40 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 5f765cdbacb..27c5cccb451 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -4160,10 +4160,10 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VI > + (match_operand:VI 4 "register_operand") > (mult:VI > (match_operand:VI 2 "register_operand") > - (match_operand:VI 3 "register_operand")) > - (match_operand:VI 4 "register_operand")) > + (match_operand:VI 3 "register_operand"))) > (match_operand:VI 5 "register_operand")))] > "TARGET_VECTOR" > { > @@ -4185,10 +4185,10 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VI > + (match_operand:VI 4 "register_operand" " vr, vr, vr") > (mult:VI > (match_operand:VI 2 "register_operand" " 0, 0, vr") > - (match_operand:VI 3 "register_operand" " vr, vr, vr")= ) > - (match_operand:VI 4 "register_operand" " vr, vr, vr")= ) > + (match_operand:VI 3 "register_operand" " vr, vr, vr")= )) > (match_dup 2)))] > "TARGET_VECTOR" > "@ > @@ -4215,10 +4215,10 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VI > + (match_operand:VI 4 "register_operand" " 0, 0, vr") > (mult:VI > (match_operand:VI 2 "register_operand" " vr, vr, vr") > - (match_operand:VI 3 "register_operand" " vr, vr, vr")= ) > - (match_operand:VI 4 "register_operand" " 0, 0, vr")= ) > + (match_operand:VI 3 "register_operand" " vr, vr, vr")= )) > (match_dup 4)))] > "TARGET_VECTOR" > "@ > @@ -4245,10 +4245,10 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VI > + (match_operand:VI 4 "vector_arith_operand" " vr, vi, = vr, vr, vr") > (mult:VI > (match_operand:VI 2 "register_operand" " vr, vr, = vi, vr, vr") > - (match_operand:VI 3 "register_operand" " vr, vr, = vr, vi, vr")) > - (match_operand:VI 4 "vector_arith_operand" " vr, vi, = vr, vr, vr")) > + (match_operand:VI 3 "register_operand" " vr, vr, = vr, vi, vr"))) > (match_operand:VI 5 "register_operand" " 0, vr, = vr, vr, vr")))] > "TARGET_VECTOR > && !rtx_equal_p (operands[2], operands[5]) > @@ -4296,11 +4296,11 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VI_QHS > + (match_operand:VI_QHS 4 "register_operand") > (mult:VI_QHS > (vec_duplicate:VI_QHS > (match_operand: 2 "reg_or_int_operand")) > - (match_operand:VI_QHS 3 "register_operand")) > - (match_operand:VI_QHS 4 "register_operand")) > + (match_operand:VI_QHS 3 "register_operand"))) > (match_operand:VI_QHS 5 "register_operand")))] > "TARGET_VECTOR" > { > @@ -4319,11 +4319,11 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VI > + (match_operand:VI 4 "register_operand" " vr, vr, vr"= ) > (mult:VI > (vec_duplicate:VI > (match_operand: 2 "register_operand" " r, r, vr"= )) > - (match_operand:VI 3 "register_operand" " 0, 0, vr"= )) > - (match_operand:VI 4 "register_operand" " vr, vr, vr"= )) > + (match_operand:VI 3 "register_operand" " 0, 0, vr"= ))) > (match_dup 3)))] > "TARGET_VECTOR" > "@ > @@ -4350,11 +4350,11 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VI > + (match_operand:VI 4 "register_operand" " 0, 0, vr"= ) > (mult:VI > (vec_duplicate:VI > (match_operand: 2 "register_operand" " r, r, vr"= )) > - (match_operand:VI 3 "register_operand" " vr, vr, vr"= )) > - (match_operand:VI 4 "register_operand" " 0, 0, vr"= )) > + (match_operand:VI 3 "register_operand" " vr, vr, vr"= ))) > (match_dup 4)))] > "TARGET_VECTOR" > "@ > @@ -4381,11 +4381,11 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VI > + (match_operand:VI 4 "vector_arith_operand" " vr, vi, = vr, vr") > (mult:VI > (vec_duplicate:VI > (match_operand: 2 "register_operand" " r, r, = r, r")) > - (match_operand:VI 3 "register_operand" " vr, vr, = vi, vr")) > - (match_operand:VI 4 "vector_arith_operand" " vr, vi, = vr, vr")) > + (match_operand:VI 3 "register_operand" " vr, vr, = vi, vr"))) > (match_operand:VI 5 "register_operand" " 0, vr, = vr, vr")))] > "TARGET_VECTOR > && !rtx_equal_p (operands[3], operands[5]) > @@ -4428,11 +4428,11 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VI_D > + (match_operand:VI_D 4 "register_operand") > (mult:VI_D > (vec_duplicate:VI_D > (match_operand: 2 "reg_or_int_operand")) > - (match_operand:VI_D 3 "register_operand")) > - (match_operand:VI_D 4 "register_operand")) > + (match_operand:VI_D 3 "register_operand"))) > (match_operand:VI_D 5 "register_operand")))] > "TARGET_VECTOR" > { > @@ -4463,12 +4463,12 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VI_D > + (match_operand:VI_D 4 "register_operand" " vr, vr, = vr") > (mult:VI_D > (vec_duplicate:VI_D > (sign_extend: > (match_operand: 2 "register_operand" " r, r, = vr"))) > - (match_operand:VI_D 3 "register_operand" " 0, 0, = vr")) > - (match_operand:VI_D 4 "register_operand" " vr, vr, = vr")) > + (match_operand:VI_D 3 "register_operand" " 0, 0, = vr"))) > (match_dup 3)))] > "TARGET_VECTOR" > "@ > @@ -4495,12 +4495,12 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VI_D > + (match_operand:VI_D 4 "register_operand" " 0, 0, = vr") > (mult:VI_D > (vec_duplicate:VI_D > (sign_extend: > (match_operand: 2 "register_operand" " r, r, = vr"))) > - (match_operand:VI_D 3 "register_operand" " vr, vr, = vr")) > - (match_operand:VI_D 4 "register_operand" " 0, 0, = vr")) > + (match_operand:VI_D 3 "register_operand" " vr, vr, = vr"))) > (match_dup 4)))] > "TARGET_VECTOR" > "@ > @@ -4527,12 +4527,12 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VI_D > + (match_operand:VI_D 4 "vector_arith_operand" " vr, = vr, vr, vr") > (mult:VI_D > (vec_duplicate:VI_D > (sign_extend: > (match_operand: 2 "register_operand" " r, = r, r, r"))) > - (match_operand:VI_D 3 "register_operand" " vr, = vr, vr, vr")) > - (match_operand:VI_D 4 "vector_arith_operand" " vr, = vr, vr, vr")) > + (match_operand:VI_D 3 "register_operand" " vr, = vr, vr, vr"))) > (match_operand:VI_D 5 "register_operand" " 0, = vr, vr, vr")))] > "TARGET_VECTOR > && !rtx_equal_p (operands[3], operands[5]) > @@ -5033,10 +5033,10 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VF > + (match_operand:VF 4 "register_operand") > (mult:VF > (match_operand:VF 2 "register_operand") > - (match_operand:VF 3 "register_operand")) > - (match_operand:VF 4 "register_operand")) > + (match_operand:VF 3 "register_operand"))) > (match_operand:VF 5 "register_operand")))] > "TARGET_VECTOR" > { > @@ -5058,10 +5058,10 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VF > + (match_operand:VF 4 "register_operand" " vr, vr, vr") > (mult:VF > (match_operand:VF 2 "register_operand" " 0, 0, vr") > - (match_operand:VF 3 "register_operand" " vr, vr, vr")= ) > - (match_operand:VF 4 "register_operand" " vr, vr, vr")= ) > + (match_operand:VF 3 "register_operand" " vr, vr, vr")= )) > (match_dup 2)))] > "TARGET_VECTOR" > "@ > @@ -5088,10 +5088,10 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VF > + (match_operand:VF 4 "register_operand" " 0, 0, vr") > (mult:VF > (match_operand:VF 2 "register_operand" " vr, vr, vr") > - (match_operand:VF 3 "register_operand" " vr, vr, vr")= ) > - (match_operand:VF 4 "register_operand" " 0, 0, vr")= ) > + (match_operand:VF 3 "register_operand" " vr, vr, vr")= )) > (match_dup 4)))] > "TARGET_VECTOR" > "@ > @@ -5118,10 +5118,10 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VF > + (match_operand:VF 4 "vector_arith_operand" " vr, vr") > (mult:VF > (match_operand:VF 2 "register_operand" " vr, vr") > - (match_operand:VF 3 "register_operand" " vr, vr")) > - (match_operand:VF 4 "vector_arith_operand" " vr, vr")) > + (match_operand:VF 3 "register_operand" " vr, vr"))) > (match_operand:VF 5 "register_operand" " 0, vr")))= ] > "TARGET_VECTOR > && !rtx_equal_p (operands[2], operands[5]) > @@ -5153,11 +5153,11 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VF > + (match_operand:VF 4 "register_operand") > (mult:VF > (vec_duplicate:VF > (match_operand: 2 "register_operand")) > - (match_operand:VF 3 "register_operand")) > - (match_operand:VF 4 "register_operand")) > + (match_operand:VF 3 "register_operand"))) > (match_operand:VF 5 "register_operand")))] > "TARGET_VECTOR" > {}) > @@ -5174,11 +5174,11 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VF > + (match_operand:VF 4 "register_operand" " vr, vr, vr"= ) > (mult:VF > (vec_duplicate:VF > (match_operand: 2 "register_operand" " f, f, vr"= )) > - (match_operand:VF 3 "register_operand" " 0, 0, vr"= )) > - (match_operand:VF 4 "register_operand" " vr, vr, vr"= )) > + (match_operand:VF 3 "register_operand" " 0, 0, vr"= ))) > (match_dup 3)))] > "TARGET_VECTOR" > "@ > @@ -5205,11 +5205,11 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VF > + (match_operand:VF 4 "register_operand" " 0, 0, vr"= ) > (mult:VF > (vec_duplicate:VF > (match_operand: 2 "register_operand" " f, f, vr"= )) > - (match_operand:VF 3 "register_operand" " vr, vr, vr"= )) > - (match_operand:VF 4 "register_operand" " 0, 0, vr"= )) > + (match_operand:VF 3 "register_operand" " vr, vr, vr"= ))) > (match_dup 4)))] > "TARGET_VECTOR" > "@ > @@ -5236,11 +5236,11 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > (plus_minus:VF > + (match_operand:VF 4 "vector_arith_operand" " vr, vr") > (mult:VF > (vec_duplicate:VF > (match_operand: 2 "register_operand" " f, f")) > - (match_operand:VF 3 "register_operand" " vr, vr")) > - (match_operand:VF 4 "vector_arith_operand" " vr, vr")) > + (match_operand:VF 3 "register_operand" " vr, vr"))) > (match_operand:VF 5 "register_operand" " 0, vr")))= ] > "TARGET_VECTOR > && !rtx_equal_p (operands[3], operands[5]) > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/bug-3.c > new file mode 100644 > index 00000000000..35b76892598 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c > @@ -0,0 +1,22 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2" } */ > + > +#include "riscv_vector.h" > +#include > + > +int main() > +{ > + int32_t a =3D 1; > + int32_t b[1] =3D {3}; > + int32_t c[1] =3D {10}; > + int32_t d[1] =3D {0}; > + vint32m1_t vb =3D __riscv_vle32_v_i32m1 (b, 1); > + vint32m1_t vc =3D __riscv_vle32_v_i32m1 (c, 1); > + vint32m1_t vd =3D __riscv_vnmsub_vx_i32m1 (vb, a, vc, 1); > + __riscv_vse32_v_i32m1 (d, vd, 1); > + if (d[0] !=3D 7){ > + printf("d[0] should be 7, but got %d\n", d[0]); > + __builtin_abort (); > + } > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/bug-4.c > new file mode 100644 > index 00000000000..62dd3f50e44 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c > @@ -0,0 +1,22 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2" } */ > + > +#include "riscv_vector.h" > +#include > + > +int main() > +{ > + float a =3D 1.0; > + float b[1] =3D {3.0}; > + float c[1] =3D {10.0}; > + float d[1] =3D {0.0}; > + vfloat32m1_t vb =3D __riscv_vle32_v_f32m1 (b, 1); > + vfloat32m1_t vc =3D __riscv_vle32_v_f32m1 (c, 1); > + vfloat32m1_t vd =3D __riscv_vfnmsub_vf_f32m1 (vb, a, vc, 1); > + __riscv_vse32_v_f32m1 (d, vd, 1); > + if (d[0] !=3D 7.0){ > + printf("d[0] should be 7.0, but got %f\n", d[0]); > + __builtin_abort (); > + } > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c b/gcc/testsu= ite/gcc.target/riscv/rvv/base/bug-5.c > new file mode 100644 > index 00000000000..e43f85a0730 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c > @@ -0,0 +1,22 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2" } */ > + > +#include "riscv_vector.h" > +#include > + > +int main() > +{ > + float a =3D 1.0; > + float b[1] =3D {3.0}; > + float c[1] =3D {10.0}; > + float d[1] =3D {0.0}; > + vfloat32m1_t vb =3D __riscv_vle32_v_f32m1 (b, 1); > + vfloat32m1_t vc =3D __riscv_vle32_v_f32m1 (c, 1); > + vfloat32m1_t vd =3D __riscv_vfmsub_vf_f32m1 (vb, a, vc, 1); > + __riscv_vse32_v_f32m1 (d, vd, 1); > + if (d[0] !=3D -7.0){ > + printf("d[0] should be -7.0, but got %f\n", d[0]); > + __builtin_abort (); > + } > + return 0; > +} > -- > 2.36.3 >