From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x933.google.com (mail-ua1-x933.google.com [IPv6:2607:f8b0:4864:20::933]) by sourceware.org (Postfix) with ESMTPS id E26EC3858D37 for ; Thu, 20 Apr 2023 10:37:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E26EC3858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x933.google.com with SMTP id l17so1918944uak.0 for ; Thu, 20 Apr 2023 03:37:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681987060; x=1684579060; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=+WCT4x4L7YsnbuyKwvcI7clz4iH2gdgmDn8lf3AYAmc=; b=DuUuFQJepMC2jFffea9p80KmMXkEahk2oyxNeJ8aXFlD3y/zt3zNlXwR32/Ba6oOSw IO0Bok2qKOejwbNPQ4agIK4eVVIHVERWNYvKzJlrhqCJ8ursZtkAaVL6YPfsAtIqvBZE Dt21HlOE7jphhpsrH5B37KPu/Rbxo2Xmwo+3Uu+p2x8TT2Dap+l7IJcqR/Vj48Dkhq1c WivwMzCj1m1ySN8i+yHZZKo9TTtjMeXlFMZ+WPYf2uOnvu9kL9QPoT9WIJjmnQo3fmcX P4zIwNshhIsIKTgdlMUfZFIlL3qWn6buJVu7PKePNUHGBjcLjwA2hKw23zKPkgBDVFT0 VoxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681987060; x=1684579060; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+WCT4x4L7YsnbuyKwvcI7clz4iH2gdgmDn8lf3AYAmc=; b=gE/rQMqUSLjf7jhGj7ThjL3MQ0Po5nWTjP/kQDQgeGlZRDizNdt/q+bZ+f3rXzQjDr /0omi/wOIZGTaJRSfxLvHc3NStRppsq15hOv1ZvoCumfipf7HKWc9VZGts36P9095oPP 1BYzaAdVDcMiuKQ75Mkygob915eDBBnK1OobGgQ7822L3JB8nvO17J9NMgVCfsEkNb0H uxaP6YIYz6EOEbt+OTFyQ1S1Qpz0qpAv6eDjwVaKXOWQjKHMYXgRPm5o9CFDRVm0i7z6 RjNQVQF5J2IqGXI54U8ykZPH65pYtKTIhEJ+SmQLAbngeMVoovaET7HlcYMFMU8yvWm1 cd7g== X-Gm-Message-State: AAQBX9fAxZCeEJyfjM2h5tPWr73Hh1MBXmj2+CEOMz963eXYgpZUr17+ mKz626PT6dhf6pu0WuwMHPhETnuIyp4FmRxVNtI= X-Google-Smtp-Source: AKy350bRGO6wbTgobSt89r/d2W/NgxbulXavKbvbV21DJShAMrLP8L9PiawzMmSFSN3gDsnXgx8uG7nCYJtb1Enilyc= X-Received: by 2002:a1f:5e4d:0:b0:432:3100:1278 with SMTP id s74-20020a1f5e4d000000b0043231001278mr347194vkb.16.1681987059848; Thu, 20 Apr 2023 03:37:39 -0700 (PDT) MIME-Version: 1.0 References: <20230419164214.1032017-1-juzhe.zhong@rivai.ai> <20230419164214.1032017-3-juzhe.zhong@rivai.ai> <97521df8-fdc6-a407-c156-234bdcb34cac@gmail.com> <10D3D856742B7B67+2023042017070185402754@rivai.ai> <3D8899AF58F4398D+2023042017345224822865@rivai.ai> <4bfc2bbd-f791-2612-1c6b-99d3546ff43a@gmail.com> <725B830310EE18AA+2023042017471261876972@rivai.ai> In-Reply-To: <725B830310EE18AA+2023042017471261876972@rivai.ai> From: Kito Cheng Date: Thu, 20 Apr 2023 18:37:28 +0800 Message-ID: Subject: Re: Re: [PATCH 2/3 V2] RISC-V: Enable basic auto-vectorization for RVV To: "juzhe.zhong@rivai.ai" Cc: Robin Dapp , gcc-patches , palmer , jeffreyalaw Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Robin: Share with you more context that I've discussed with Ju-Zhe, and look for comments from you :) There is 3 different auto vectorization flavor: - VLA - VLS fixed-vlmax (Name TBD) - (Traditional) VLS I think I don't need to explain too much on VLA. So let we focus on second and third: VLS fixed-vlmax, that's something like -mriscv-vector-bits=3D or -msve-vector-bits, assume VLEN is a static length, and evaluate scalable vector mode as fixed length vector mode (e.g. evaluate (8x + 8) byte to 16 byte), so that stack allocation could be done by static instead computed by vlenb register, and vlvmax could be evaluate to a static value too, but the code generated by this mode is not portable, when you compile with -mriscv-vector-bits=3D128, then the code can't run on machine which VLEN is not exactly equal to 128. (Traditional) VLS, vectorized to something like int32x4_t, stack allocation can be determined in static too since the size is fixed, but size of vector register size is still a poly_int16 value (scalable vector), not evaluated to fixed length vector like VLS fixed-vlmax mode, this mode could be useful to handle those loop can't vectorized by VLA mode, or used by SLP vectorizor, and this mode is more portable than VLS fixed-vlmax mode since it only require VLEN is larger than specific length, rather than require must equal to specific length. On Thu, Apr 20, 2023 at 5:47=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > Ahhh. These compile options are not finalized. > I just ask kito provide me some compile option that I can specify LMUL &&= auto-vectorization mode && vector-length (scalable or fixed-length) > in order to have chances test auto-vectorizaiton fully for example: fully= testing LMUL =3D 1/2/4/8 auto-vectorization (You can see the codes in rvv.= exp). > Then, he let me add --param options. > > I can change compile option as you suggested. > > Thanks. > > > juzhe.zhong@rivai.ai > > From: Robin Dapp > Date: 2023-04-20 17:42 > To: juzhe.zhong@rivai.ai; kito.cheng > CC: gcc-patches; palmer; jeffreyalaw > Subject: Re: [PATCH 2/3 V2] RISC-V: Enable basic auto-vectorization for R= VV > > Can you give more comments about Robin's opinion that he want to change= into > > "fixed" vs "varying" or "fixed vector size" vs "dynamic vector size" ? > > It's not necessary to decide on this now as --params are not supposed > to be stable and can be changed quickly. I was just curious if this had > already been discussed or finalized elsewhere. > > Regards > Robin >