From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <SRS0=Eymp=54=gmail.com=npickito@sourceware.org>
Received: from mail-vs1-xe32.google.com (mail-vs1-xe32.google.com [IPv6:2607:f8b0:4864:20::e32])
	by sourceware.org (Postfix) with ESMTPS id 35C4A3894C2F
	for <gcc-patches@gcc.gnu.org>; Tue, 31 Jan 2023 16:49:50 +0000 (GMT)
DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 35C4A3894C2F
Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com
Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com
Received: by mail-vs1-xe32.google.com with SMTP id i185so16713893vsc.6
        for <gcc-patches@gcc.gnu.org>; Tue, 31 Jan 2023 08:49:50 -0800 (PST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=gmail.com; s=20210112;
        h=cc:to:subject:message-id:date:from:in-reply-to:references
         :mime-version:from:to:cc:subject:date:message-id:reply-to;
        bh=AGUjuX9lE9genVDqM0wg4k+gOqxPwDLRsbgoJ/HQBiQ=;
        b=EPxgfA5B/O3LbJQI7z9VGeTEgC3fHuqlYpVAVR6yrv0Gh6mfrmHXUJysqEImTro4zw
         jb7lsT9OAoX+oIQjGAZiof1omF00jlgMJ0Sw3ty5hqxmrtESDfv2gCD4z0MpSVWaur6Y
         D7Pslantk1UJ0nIrEmD+SYydPp25pusvrJtxWMbGZ9NDLhOyUOeKoNRb/iLHi+O68irO
         tYY6uCGebiaS36mGfu3amvS3eFEt2eLRzpIUghUfjRR3T1puVAOcEOIfcp1uWCOgXeHo
         /ySFeSXch9luvAFL0fmdy126vJQp4ZYqybIv4pzittocmaestV+7dD4sxWW44GzBgN7R
         MsGQ==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=1e100.net; s=20210112;
        h=cc:to:subject:message-id:date:from:in-reply-to:references
         :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id
         :reply-to;
        bh=AGUjuX9lE9genVDqM0wg4k+gOqxPwDLRsbgoJ/HQBiQ=;
        b=DRkF/mK//HQkr1sG+S+by/yX7nog1ljw7fM2dX7DV7uez8AEJVNNx0WYAOul2G9sur
         mg9E1nMeAi/lh/I0Sd2a3qS60NAF6NCpHFI44v0ZPlJFfTFhD7CRnI1j6JUBsgpRKfdW
         d0pZw5EBAbyJj0UErGgC0fNL1O0Djk67308nxcg24QeRinv98PvLWge/jCwq/tSJRGS2
         w0Bg1yYg6r1UJzb4UQozEcpv6qtenlW5v6+3RGF+CO5thu0eQcYz6TuC/N2kUkuxeRgB
         L1tsjbQSkGZmQOjrx/XOwzXCiQwtbnmI+V6Fw7Cf8VTQzM+UoG2Nd32LziBMl8PeBdH4
         aqdA==
X-Gm-Message-State: AFqh2kpP3Iij9C+3p5kcYva6VXZpy2ffG/9xOLq3pk23BZ19P07yfcfi
	QeoZulJQA33WKYGGbXmFKGOUeJRRHnDghFFLMkPikvQqQrM=
X-Google-Smtp-Source: AMrXdXvUGfk/DHIfZKL8g87PuPPE7eLpknOFWNJ18oWafn0Ag2Tj8AaQHyLB6X1TZSuTtOC+1bE6jBlQ3wYoCVauCHM=
X-Received: by 2002:a05:6102:6c2:b0:3ce:bced:178 with SMTP id
 m2-20020a05610206c200b003cebced0178mr7438263vsg.84.1675183788854; Tue, 31 Jan
 2023 08:49:48 -0800 (PST)
MIME-Version: 1.0
References: <20230131130517.322011-1-juzhe.zhong@rivai.ai>
In-Reply-To: <20230131130517.322011-1-juzhe.zhong@rivai.ai>
From: Kito Cheng <kito.cheng@gmail.com>
Date: Wed, 1 Feb 2023 00:49:36 +0800
Message-ID: <CA+yXCZB7LZQHDsK3VTRCDi5krn=vZBd72jCsLxj4Q8NXA3K+rQ@mail.gmail.com>
Subject: Re: [PATCH] RISC-V: Add vor.vv C++ API tests
To: juzhe.zhong@rivai.ai
Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com
Content-Type: text/plain; charset="UTF-8"
X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org
List-Id: <gcc-patches.gcc.gnu.org>

committed, thanks!

On Tue, Jan 31, 2023 at 9:06 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
>         * g++.target/riscv/rvv/base/vor_vv-1.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv-2.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv-3.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv_mu-1.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv_mu-2.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv_mu-3.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv_tu-1.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv_tu-2.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv_tu-3.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv_tum-1.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv_tum-2.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv_tum-3.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv_tumu-1.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv_tumu-2.C: New test.
>         * g++.target/riscv/rvv/base/vor_vv_tumu-3.C: New test.
>
> ---
>  .../g++.target/riscv/rvv/base/vor_vv-1.C      | 578 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vor_vv-2.C      | 578 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vor_vv-3.C      | 578 ++++++++++++++++++
>  .../g++.target/riscv/rvv/base/vor_vv_mu-1.C   | 292 +++++++++
>  .../g++.target/riscv/rvv/base/vor_vv_mu-2.C   | 292 +++++++++
>  .../g++.target/riscv/rvv/base/vor_vv_mu-3.C   | 292 +++++++++
>  .../g++.target/riscv/rvv/base/vor_vv_tu-1.C   | 292 +++++++++
>  .../g++.target/riscv/rvv/base/vor_vv_tu-2.C   | 292 +++++++++
>  .../g++.target/riscv/rvv/base/vor_vv_tu-3.C   | 292 +++++++++
>  .../g++.target/riscv/rvv/base/vor_vv_tum-1.C  | 292 +++++++++
>  .../g++.target/riscv/rvv/base/vor_vv_tum-2.C  | 292 +++++++++
>  .../g++.target/riscv/rvv/base/vor_vv_tum-3.C  | 292 +++++++++
>  .../g++.target/riscv/rvv/base/vor_vv_tumu-1.C | 292 +++++++++
>  .../g++.target/riscv/rvv/base/vor_vv_tumu-2.C | 292 +++++++++
>  .../g++.target/riscv/rvv/base/vor_vv_tumu-3.C | 292 +++++++++
>  15 files changed, 5238 insertions(+)
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-3.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-1.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-2.C
>  create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-3.C
>
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-1.C
> new file mode 100644
> index 00000000000..e12c93cf89b
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-1.C
> @@ -0,0 +1,578 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vor(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vor(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vor(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vor(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vor(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vor(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vor(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vor(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vor(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vor(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vor(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vor(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vor(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vor(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vor(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vor(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,vl);
> +}
> +
> +
> +vint8mf8_t test___riscv_vor(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vor(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vor(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vor(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vor(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vor(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vor(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vor(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vor(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vor(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vor(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vor(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vor(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vor(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vor(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vor(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vor(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-2.C
> new file mode 100644
> index 00000000000..fefda8e98d4
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-2.C
> @@ -0,0 +1,578 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vor(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vor(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vor(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vor(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vor(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vor(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vor(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vor(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vor(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vor(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vor(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vor(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vor(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vor(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vor(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vor(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,31);
> +}
> +
> +
> +vint8mf8_t test___riscv_vor(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vor(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vor(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vor(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vor(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vor(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vor(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vor(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vor(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vor(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vor(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vor(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vor(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vor(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vor(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vor(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vor(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-3.C
> new file mode 100644
> index 00000000000..0344c15cff9
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-3.C
> @@ -0,0 +1,578 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vor(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vor(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vor(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vor(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vor(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vor(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vor(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vor(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vor(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vor(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vor(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vor(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vor(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vor(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vor(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vor(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(op1,op2,32);
> +}
> +
> +
> +vint8mf8_t test___riscv_vor(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vor(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vor(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vor(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vor(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vor(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vor(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vor(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vor(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vor(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vor(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vor(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vor(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vor(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vor(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vor(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vor(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor(mask,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-1.C
> new file mode 100644
> index 00000000000..ffbbdda7ea6
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-1.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-2.C
> new file mode 100644
> index 00000000000..c77c0ba4adb
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-2.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-3.C
> new file mode 100644
> index 00000000000..5b42aa67b2f
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-3.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-1.C
> new file mode 100644
> index 00000000000..656a591aa74
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-1.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vor_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vor_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vor_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vor_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vor_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vor_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vor_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vor_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vor_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vor_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vor_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vor_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vor_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vor_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vor_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vor_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-2.C
> new file mode 100644
> index 00000000000..102f8773630
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-2.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vor_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vor_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vor_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vor_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vor_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vor_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vor_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vor_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vor_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vor_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vor_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vor_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vor_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vor_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vor_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vor_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-3.C
> new file mode 100644
> index 00000000000..f1788320ed3
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-3.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vor_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vor_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vor_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vor_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vor_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vor_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vor_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vor_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vor_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vor_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vor_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vor_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vor_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vor_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vor_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vor_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tu(merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-1.C
> new file mode 100644
> index 00000000000..c2793716d6f
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-1.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-2.C
> new file mode 100644
> index 00000000000..b0d8a83fc82
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-2.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-3.C
> new file mode 100644
> index 00000000000..183f63dbeb7
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-3.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-1.C
> new file mode 100644
> index 00000000000..1f37498ebdc
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-1.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-2.C
> new file mode 100644
> index 00000000000..90c157a4bc8
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-2.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-3.C
> new file mode 100644
> index 00000000000..65286e2e4a5
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-3.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> --
> 2.36.3
>
>