From: Kito Cheng <kito.cheng@gmail.com>
To: Lehua Ding <lehua.ding@rivai.ai>
Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai,
rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com
Subject: Re: [PATCH 2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed
Date: Mon, 7 Aug 2023 14:53:57 +0800 [thread overview]
Message-ID: <CA+yXCZB86kUzN5b5e+aMFQbrwz6MVyhw0d_4Kq7i7etY3+2Rig@mail.gmail.com> (raw)
In-Reply-To: <20230720090126.2976103-3-lehua.ding@rivai.ai>
> + machine_mode m1_mode = TARGET_VECTOR_ELEN_64
> + ? (TARGET_MIN_VLEN >= 128 ? VNx2DImode : VNx1DImode)
> + : VNx1SImode;
This should update since JuZhe has update the mode system :P
> @@ -5907,7 +6057,7 @@ riscv_expand_epilogue (int style)
> Start off by assuming that no registers need to be restored. */
> struct riscv_frame_info *frame = &cfun->machine->frame;
> unsigned mask = frame->mask;
> - HOST_WIDE_INT step2 = 0;
> + poly_int64 step2 = 0;
I saw we check `step2.to_constant () > 0` later, does it mean step2 is
always a scalar rather than a poly number?
If so, I would suggest keeping HOST_WIDE_INT if possible.
> @@ -6058,10 +6218,10 @@ riscv_expand_epilogue (int style)
> riscv_emit_stack_tie ();
>
> /* Deallocate the final bit of the frame. */
> - if (step2 > 0)
> + if (step2.to_constant () > 0)
> {
> insn = emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
> - GEN_INT (step2)));
> + GEN_INT (step2.to_constant ())));
>
> rtx dwarf = NULL_RTX;
> rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
next prev parent reply other threads:[~2023-08-07 6:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 9:01 [PATCH 0/3] RISC-V: Add an experimental vector calling convention Lehua Ding
2023-07-20 9:01 ` [PATCH 1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns Lehua Ding
2023-08-07 8:51 ` Kito Cheng
2023-08-10 7:08 ` Lehua Ding
2023-07-20 9:01 ` [PATCH 2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed Lehua Ding
2023-08-07 6:53 ` Kito Cheng [this message]
2023-07-20 9:01 ` [PATCH 3/3] RISC-V: Part-3: Output .variant_cc directive for vector function Lehua Ding
2023-08-07 7:31 [PATCH 2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed Lehua Ding
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