From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x92c.google.com (mail-ua1-x92c.google.com [IPv6:2607:f8b0:4864:20::92c]) by sourceware.org (Postfix) with ESMTPS id 0CB593858D35 for ; Mon, 7 Aug 2023 06:54:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0CB593858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x92c.google.com with SMTP id a1e0cc1a2514c-79aa01cc971so1557763241.0 for ; Sun, 06 Aug 2023 23:54:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1691391248; x=1691996048; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=WtHh5q4oAq95+8DESGGNsI8yK5S27qAHH2QZ2j4UsbY=; b=mudoqfc/vDWUiscmkTKgbtid+q04zBIKyOoJUd7c3eRFaCwrca2G0gEhfOifKWsLE5 7r89c4GQsCWki+ePidXX4Qkqv+JNoRq9y8z/AU4rr9FTNV2UZptNIOILqzNYMKc+8rAB HGzdr4LWbsxcSEPlZaewTQpa9ulaPUvZ2hgK/8j7vmkmAPCwZYNrYcmpiWxfa/Nhak00 dSJ0q8w9ghmInsijZh17ELmeUsWS9LLrPAbbdoAeCL9ZHzsxL9SqwHwbmDKJi1NR4kvI bPh1SKR0cLC9XPSAtREgHI5o/WWFOJzsPo3Tft5An+4t5kK8v8orweZPPbqyOGhaaWtB g0lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691391248; x=1691996048; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=WtHh5q4oAq95+8DESGGNsI8yK5S27qAHH2QZ2j4UsbY=; b=QJ/xDzD/m87IJ2Q/tnkekrCCq7k5H0xpCObR6Ob0T+k8hnqkmvV5Zynp7C3zRxzJ4v MlgpUcNMUUJODMAbJPoHNgXqAaM6KVN3hp6VU5oUngicOnFqqYHifq8NHp4BbDgS0Su5 UCX9XMzkeN5tUYXYOjgVWr84PrG+Fd512PMpAMqrJBG25UaNz9SU70UPsG3w3iY4is7j g/aAUzrDCr+q1cTBhmwjbNM/0BHCbtM2FRvgYzK0XfGsoLXnG4O93Ls1eU2i0EX+pc0s BC5VooU7yXA9plp0IWp+DkbOxlSp+LoP3/snHLrscw+AvvEzXONACbRPjw/19/SprH53 +FiQ== X-Gm-Message-State: AOJu0Yw0rFKVWIqsFGlHEihPbneN+q9HSakrGv5QTAfn0+PSmjOuxBO5 2yrseaTjsaqmglsa0Yv+KlujT5oB9+TYN5hDE7HkflWtIZs= X-Google-Smtp-Source: AGHT+IGUgivvmXvxMB4zDIAPdHvVuk34pKqPV9lK/gWl/6VIw7tlxQWIggfEzgnLNc35z6mbRbfKYida53uGxesLEq0= X-Received: by 2002:a1f:e707:0:b0:486:3e05:da14 with SMTP id e7-20020a1fe707000000b004863e05da14mr3795025vkh.12.1691391248189; Sun, 06 Aug 2023 23:54:08 -0700 (PDT) MIME-Version: 1.0 References: <20230720090126.2976103-1-lehua.ding@rivai.ai> <20230720090126.2976103-3-lehua.ding@rivai.ai> In-Reply-To: <20230720090126.2976103-3-lehua.ding@rivai.ai> From: Kito Cheng Date: Mon, 7 Aug 2023 14:53:57 +0800 Message-ID: Subject: Re: [PATCH 2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed To: Lehua Ding Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > + machine_mode m1_mode = TARGET_VECTOR_ELEN_64 > + ? (TARGET_MIN_VLEN >= 128 ? VNx2DImode : VNx1DImode) > + : VNx1SImode; This should update since JuZhe has update the mode system :P > @@ -5907,7 +6057,7 @@ riscv_expand_epilogue (int style) > Start off by assuming that no registers need to be restored. */ > struct riscv_frame_info *frame = &cfun->machine->frame; > unsigned mask = frame->mask; > - HOST_WIDE_INT step2 = 0; > + poly_int64 step2 = 0; I saw we check `step2.to_constant () > 0` later, does it mean step2 is always a scalar rather than a poly number? If so, I would suggest keeping HOST_WIDE_INT if possible. > @@ -6058,10 +6218,10 @@ riscv_expand_epilogue (int style) > riscv_emit_stack_tie (); > > /* Deallocate the final bit of the frame. */ > - if (step2 > 0) > + if (step2.to_constant () > 0) > { > insn = emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, > - GEN_INT (step2))); > + GEN_INT (step2.to_constant ()))); > > rtx dwarf = NULL_RTX; > rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,