From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa33.google.com (mail-vk1-xa33.google.com [IPv6:2607:f8b0:4864:20::a33]) by sourceware.org (Postfix) with ESMTPS id E857438582BD for ; Thu, 26 Jan 2023 19:13:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E857438582BD Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vk1-xa33.google.com with SMTP id az23so1360346vkb.8 for ; Thu, 26 Jan 2023 11:13:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=D2t5DUAZ+ZmFV5aVXnrfNnbfp5oIxYFmH3GMN3GOyto=; b=Oi/p+RWe4xUEubwuY3sgz5+bp3AqP0/2RRhsRQo96EV1PemIckZZaHwnxn7TMlRrb5 yp+GLCg6X8yZu8KlpQYHA1k79icwhIYlwNawx97eM4dE04ubCH8FWg3/Gfj9gcGRZdIh HvSV+fvacQPFK/IZsfBZgkvryipbbx1AptscURDPd+p6YBD8dUwBC0DkbgnZEbLtr5bG U4wMAjsHc03i9ogbSJTMGhU0aQ67Oz9+3bqbAYo+FppRtQDPC6TAyMW5w9KMEw+vppJ/ ixQQ1thdfdNIrV155/6v2WTZctk7rfwd+nyyDi8JqUIZY7IVO9h7OX0pheABSNVVnr/p Osaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=D2t5DUAZ+ZmFV5aVXnrfNnbfp5oIxYFmH3GMN3GOyto=; b=CcWjjNHO7kQQOJJ4z1ezy+BiYslyyS5982fJd1MYDbihvBD0kqNxyp46/5yoD79zVh /zwuCCRbQrqzQo9/rrCl6yNhBB2q7D6zy/yAEa1LGnSd2Ib9lqXcRMrofpHgY+mSXzKA NIA/uByogle9XTcEBoUFxH2sXFYtzsNTkH/hWVZOTL+4sfyFC4dX84x5xaROSddLKSbI M0mawNQksha+dI553brhufAP89Cm2HGq/zQ1ddImkgVxKzWSWJC3L87hDGg/XvUtdzPQ jOZVPEtrA5Ug3XnAU5Ntwu10+gUiJzEzU9+qi4Obrn6rEO7+aB7DcNvZyvjZMZMIOB+m Z/Qg== X-Gm-Message-State: AFqh2krtSNAp4aKJVDhjjB7TOiGBEAuUjixjCAOZwKW4BSRZsIdyRM7B P3dBzMcmZcic3D5uc1EJ0O+18jYUbo1MZgoqGtI= X-Google-Smtp-Source: AMrXdXuV231Of9rLs9qzKtabiMg8ZBaIItt60Gq3qKTku/dKwbDAdmNHnq7WZeph+oeylO5Y5teSGxQ0sWjRXk6+kTw= X-Received: by 2002:a05:6122:91d:b0:3e1:a746:2b9e with SMTP id j29-20020a056122091d00b003e1a7462b9emr4399765vka.5.1674760393031; Thu, 26 Jan 2023 11:13:13 -0800 (PST) MIME-Version: 1.0 References: <20230103065530.142443-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230103065530.142443-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Fri, 27 Jan 2023 03:13:01 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zero, zero incorrectly To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com Content-Type: multipart/alternative; boundary="0000000000004f849a05f32f8a01" X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000004f849a05f32f8a01 Content-Type: text/plain; charset="UTF-8" committed, thanks. On Tue, Jan 3, 2023 at 2:56 PM wrote: > From: Ju-Zhe Zhong > > Currently we support this optimization: > > bb 0: > vsetvli a5,zero,e32,mf2 > bb 1: > vsetvli a5,zero,e64,m1 --> vsetvli zero,zero,e64,m1 > > According RVV ISA, we can do this optimization only if both RATIO and AVL > are equal. > However, current VSETVL PASS missed the check of AVL. This patch add this > condition > check to fix bugs. > > gcc/ChangeLog: > > * config/riscv/riscv-vsetvl.cc > (vector_infos_manager::all_same_avl_p): New function. > (pass_vsetvl::can_refine_vsetvl_p): Add AVL check. > (pass_vsetvl::commit_vsetvls): Ditto. > * config/riscv/riscv-vsetvl.h: New function declaration. > > --- > gcc/config/riscv/riscv-vsetvl.cc | 35 ++++++++++++++++++++++++++++---- > gcc/config/riscv/riscv-vsetvl.h | 3 +++ > 2 files changed, 34 insertions(+), 4 deletions(-) > > diff --git a/gcc/config/riscv/riscv-vsetvl.cc > b/gcc/config/riscv/riscv-vsetvl.cc > index ce1e9e3609f..1afe76304fb 100644 > --- a/gcc/config/riscv/riscv-vsetvl.cc > +++ b/gcc/config/riscv/riscv-vsetvl.cc > @@ -1440,6 +1440,29 @@ vector_infos_manager::all_same_ratio_p (sbitmap > bitdata) const > return true; > } > > +bool > +vector_infos_manager::all_same_avl_p (const basic_block cfg_bb, > + sbitmap bitdata) const > +{ > + if (bitmap_empty_p (bitdata)) > + return false; > + > + const auto &block_info = vector_block_infos[cfg_bb->index]; > + if (!block_info.local_dem.demand_p (DEMAND_AVL)) > + return true; > + > + avl_info avl = block_info.local_dem.get_avl_info (); > + unsigned int bb_index; > + sbitmap_iterator sbi; > + > + EXECUTE_IF_SET_IN_BITMAP (bitdata, 0, bb_index, sbi) > + { > + if (vector_exprs[bb_index]->get_avl_info () != avl) > + return false; > + } > + return true; > +} > + > size_t > vector_infos_manager::expr_set_num (sbitmap bitdata) const > { > @@ -2113,6 +2136,10 @@ pass_vsetvl::can_refine_vsetvl_p (const basic_block > cfg_bb, uint8_t ratio) const > m_vector_manager->vector_avin[cfg_bb->index])) > return false; > > + if (!m_vector_manager->all_same_avl_p ( > + cfg_bb, m_vector_manager->vector_avin[cfg_bb->index])) > + return false; > + > size_t expr_id > = bitmap_first_set_bit (m_vector_manager->vector_avin[cfg_bb->index]); > if (m_vector_manager->vector_exprs[expr_id]->get_ratio () != ratio) > @@ -2227,11 +2254,11 @@ pass_vsetvl::commit_vsetvls (void) > > insn_info *insn = require->get_insn (); > vector_insn_info prev_info = vector_insn_info (); > - if (m_vector_manager->all_same_ratio_p ( > - m_vector_manager->vector_avout[eg->src->index])) > + sbitmap bitdata = > m_vector_manager->vector_avout[eg->src->index]; > + if (m_vector_manager->all_same_ratio_p (bitdata) > + && m_vector_manager->all_same_avl_p (eg->dest, bitdata)) > { > - size_t first = bitmap_first_set_bit ( > - m_vector_manager->vector_avout[eg->src->index]); > + size_t first = bitmap_first_set_bit (bitdata); > prev_info = *m_vector_manager->vector_exprs[first]; > } > > diff --git a/gcc/config/riscv/riscv-vsetvl.h > b/gcc/config/riscv/riscv-vsetvl.h > index 6f27004fab1..c8218a6ff00 100644 > --- a/gcc/config/riscv/riscv-vsetvl.h > +++ b/gcc/config/riscv/riscv-vsetvl.h > @@ -333,6 +333,9 @@ public: > /* Get all relaxer expression id for corresponding vector info. */ > auto_vec get_all_available_exprs (const vector_insn_info &) > const; > > + /* Return true if all expression set in bitmap are same AVL. */ > + bool all_same_avl_p (const basic_block, sbitmap) const; > + > /* Return true if all expression set in bitmap are same ratio. */ > bool all_same_ratio_p (sbitmap) const; > > -- > 2.36.3 > > --0000000000004f849a05f32f8a01--