From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe35.google.com (mail-vs1-xe35.google.com [IPv6:2607:f8b0:4864:20::e35]) by sourceware.org (Postfix) with ESMTPS id EF3EB385840F for ; Fri, 24 Feb 2023 08:09:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EF3EB385840F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe35.google.com with SMTP id f23so19994239vsa.13 for ; Fri, 24 Feb 2023 00:09:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=BJ9mUGnHxWjhVMFOleyRxlHDFgM4C42paib8hZ1Y54c=; b=mJsBz0r9QQSBnQH5pvJbZSxkKiTaBtrBUKCeEpd+bu/ZKbW8dFRF6FxIoDoqXKaka0 vLU7kLPe0O4EhU8Um3JAKSLxlEZHUpg1/Zgjt+v9fP8SdgPmb6eh22CL2wBFfnJ3OxpR TQTPYbB4SEuo5qBRPmDLROcOO6fiYGEElUoDSNSqN4TpIkruSYV5AhU9+WrCJU/ZObQW J2WefLuU42kRLxfIid80VPZPs/pbcTQMELFx4+0Oz3bCzGMkBPAX0NP67G7Ak2Q+odWx V2NvquDWEjyDpkoYENMQOLCLZ4iaNvG2fplC9T0/2y/mCFg5sH0+RRxPM5f8lheBh22I TN2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BJ9mUGnHxWjhVMFOleyRxlHDFgM4C42paib8hZ1Y54c=; b=saqLzSlzLxE3AyNKARcNzD9yP/+VpcHOg6/UEjY2fXmrnAr6Fz6eMoeg1i6OxW1L86 geTtMyb3oBXlY4f4+fJgKwn/6Ht72nUxhFiM+j0MtAX2dV6b+6IVfhRFDjjAYtFJGJZj UkI6SH2tk32jK9WPSs9ZxYPUZq+1CgtfVVkC1PKulMriv93f6DCMcmU1zCWdB/33gTfN 5CGPipnYg+oTgjUKbDerCse2UeEvjmk8U/VSz8NQh/cDKYI2DKePEu1hOBUmraf7Wy/N i8oM2Z0yXEW9GUie2AL0judlh/uNTY8FWt20bGIVk19O/bzEY0lmnautNzlnG5fvCOrY CR6w== X-Gm-Message-State: AO0yUKW0fpy5nF5A4vpoRz6JxHBIAqobSR1L5A4NKdpqjZXAiD93SP3X AT0dZbSfpcBit2iWoFSFZP5+XHwhzXEJ9XBJpNI= X-Google-Smtp-Source: AK7set/tqsaJtsjiLic2FfqO7K4Uosl0TsgS44xyikU6fRFK5wI12Ekd8TVlOnVamqhuqcNHOH1OE5796PH4TCx2DRI= X-Received: by 2002:ac5:c7c4:0:b0:411:ff57:d3b9 with SMTP id e4-20020ac5c7c4000000b00411ff57d3b9mr1918382vkn.2.1677226150990; Fri, 24 Feb 2023 00:09:10 -0800 (PST) MIME-Version: 1.0 References: <20230224055127.2500953-1-christoph.muellner@vrull.eu> In-Reply-To: <20230224055127.2500953-1-christoph.muellner@vrull.eu> From: Kito Cheng Date: Fri, 24 Feb 2023 16:08:59 +0800 Message-ID: Subject: Re: [PATCH v3 00/11] RISC-V: Add XThead* extension support To: Christoph Muellner Cc: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Christoph: OK for trunk for the 1~8, feel free to commit 1~8 after you address those minor comments, and could you also prepare release notes for those extensions? And 9~11 needs to take a few more rounds of review and test. On Fri, Feb 24, 2023 at 1:52 PM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This series introduces support for the T-Head specific RISC-V ISA extensi= ons > which are available e.g. on the T-Head XuanTie C906. > > The ISA spec can be found here: > https://github.com/T-head-Semi/thead-extension-spec > > This series adds support for the following XThead* extensions: > * XTheadBa > * XTheadBb > * XTheadBs > * XTheadCmo > * XTheadCondMov > * XTheadFMemIdx > * XTheadFmv > * XTheadInt > * XTheadMac > * XTheadMemIdx > * XTheadMemPair > * XTheadSync > > All extensions are properly integrated and the included tests > demonstrate the improvements of the generated code. > > The series also introduces support for "-mcpu=3Dthead-c906", which also > enables all available XThead* ISA extensions of the T-Head C906. > > All patches have been tested and don't introduce regressions for RV32 or = RV64. > The patches have also been tested with SPEC CPU2017 on QEMU and real HW > (D1 board). > > Support patches for these extensions for Binutils, QEMU, and LLVM have > already been merged in the corresponding upstream projects. > > Changes in v3: > - Bugfix in XTheadBa > - Rewrite of XTheadMemPair > - Inclusion of XTheadMemIdx and XTheadFMemIdx > > Christoph M=C3=BCllner (9): > riscv: Add basic XThead* vendor extension support > riscv: riscv-cores.def: Add T-Head XuanTie C906 > riscv: thead: Add support for the XTheadBa ISA extension > riscv: thead: Add support for the XTheadBs ISA extension > riscv: thead: Add support for the XTheadBb ISA extension > riscv: thead: Add support for the XTheadCondMov ISA extensions > riscv: thead: Add support for the XTheadMac ISA extension > riscv: thead: Add support for the XTheadFmv ISA extension > riscv: thead: Add support for the XTheadMemPair ISA extension > > moiz.hussain (2): > riscv: thead: Add support for the XTheadMemIdx ISA extension > riscv: thead: Add support for the XTheadFMemIdx ISA extension > > gcc/common/config/riscv/riscv-common.cc | 26 + > gcc/config/riscv/bitmanip.md | 52 +- > gcc/config/riscv/constraints.md | 43 + > gcc/config/riscv/iterators.md | 4 + > gcc/config/riscv/peephole.md | 56 + > gcc/config/riscv/riscv-cores.def | 4 + > gcc/config/riscv/riscv-opts.h | 29 + > gcc/config/riscv/riscv-protos.h | 28 +- > gcc/config/riscv/riscv.cc | 1090 +++++++++++++++-- > gcc/config/riscv/riscv.h | 8 +- > gcc/config/riscv/riscv.md | 169 ++- > gcc/config/riscv/riscv.opt | 3 + > gcc/config/riscv/thead.md | 351 ++++++ > .../gcc.target/riscv/mcpu-thead-c906.c | 28 + > .../gcc.target/riscv/xtheadba-addsl.c | 55 + > gcc/testsuite/gcc.target/riscv/xtheadba.c | 14 + > gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 20 + > .../gcc.target/riscv/xtheadbb-extu-2.c | 22 + > .../gcc.target/riscv/xtheadbb-extu.c | 22 + > gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c | 18 + > gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 45 + > .../gcc.target/riscv/xtheadbb-srri.c | 21 + > gcc/testsuite/gcc.target/riscv/xtheadbb.c | 14 + > gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 + > gcc/testsuite/gcc.target/riscv/xtheadbs.c | 14 + > gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 14 + > .../riscv/xtheadcondmov-mveqz-imm-eqz.c | 38 + > .../riscv/xtheadcondmov-mveqz-imm-not.c | 38 + > .../riscv/xtheadcondmov-mveqz-reg-eqz.c | 38 + > .../riscv/xtheadcondmov-mveqz-reg-not.c | 38 + > .../riscv/xtheadcondmov-mvnez-imm-cond.c | 38 + > .../riscv/xtheadcondmov-mvnez-imm-nez.c | 38 + > .../riscv/xtheadcondmov-mvnez-reg-cond.c | 38 + > .../riscv/xtheadcondmov-mvnez-reg-nez.c | 38 + > .../gcc.target/riscv/xtheadcondmov.c | 14 + > .../riscv/xtheadfmemidx-fldr-fstr.c | 58 + > .../gcc.target/riscv/xtheadfmemidx.c | 14 + > .../gcc.target/riscv/xtheadfmv-fmv.c | 24 + > gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 + > gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 + > .../gcc.target/riscv/xtheadmac-mula-muls.c | 43 + > gcc/testsuite/gcc.target/riscv/xtheadmac.c | 14 + > .../gcc.target/riscv/xtheadmemidx-ldi-sdi.c | 72 ++ > .../riscv/xtheadmemidx-ldr-str-32.c | 23 + > .../riscv/xtheadmemidx-ldr-str-64.c | 53 + > .../gcc.target/riscv/xtheadmemidx-macros.h | 110 ++ > gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 14 + > .../gcc.target/riscv/xtheadmempair-1.c | 98 ++ > .../gcc.target/riscv/xtheadmempair-2.c | 84 ++ > .../gcc.target/riscv/xtheadmempair-3.c | 29 + > .../gcc.target/riscv/xtheadmempair.c | 13 + > gcc/testsuite/gcc.target/riscv/xtheadsync.c | 14 + > 52 files changed, 3048 insertions(+), 124 deletions(-) > create mode 100644 gcc/config/riscv/thead.md > create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-im= m-eqz.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-im= m-not.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-re= g-eqz.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-re= g-not.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-im= m-cond.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-im= m-nez.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-re= g-cond.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-re= g-nez.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-fldr-fst= r.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac-mula-muls.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-ldi-sdi.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-ldr-str-3= 2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-ldr-str-6= 4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-macros.h > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair.c > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c > > -- > 2.39.2 >