From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe34.google.com (mail-vs1-xe34.google.com [IPv6:2607:f8b0:4864:20::e34]) by sourceware.org (Postfix) with ESMTPS id 504E0385843A for ; Sun, 2 Apr 2023 08:33:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 504E0385843A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe34.google.com with SMTP id d18so22822621vsv.11 for ; Sun, 02 Apr 2023 01:33:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680424434; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=990Cikq8o4VYmcnVZjqi7Sp/f0q3I7VdtL/w2RDPoUs=; b=Ldt8jr4GTBAh9LIrq400X4yfY4fGUIPjGnTG1U9nVBXk0j3VzWKSWy+4N3qHFmEGV8 1JFQYRTHpVo6q/SofwVILi7oPmtM8yPkE/Q6wzLdQW3g9S2Y52N6kwRjEhGjpd/GOpfN BTUJy5G9MqunRzWjlfKT1SZbbjCgEW1jlBfP+yT5iNjEheDmwSdTAIF+Wpw1RIvMFsg3 c1njfPS+/HK3Y8HPloqUkWcnmDc6yOOLQAfy/63NLeV2Tm1CxAOPAMNl/TXX/JNgBQLQ TdQ+hp0bMyFFN9cQWUOdAdurIj+K+CJ4cKuO2XE9NF+MPn7BhjE4YgFYtGSTMm50yzUj X3Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680424434; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=990Cikq8o4VYmcnVZjqi7Sp/f0q3I7VdtL/w2RDPoUs=; b=HVJYM59Zcdt9SG9Fde43iMSEwBnTonbQoh3NPKEPjqKRu3M/Ncjp4jHfVB/EKE3gg4 +5D5XET6U4jcq9yroZLm7ISwYXvq+wCo0jkOkMpCDsj0EweBTUriq/QXiw7cRZ9oNSIx QUFg0dPboMvalQLDlqYHQEXEv3MgWST/jrNDkngi//OD4nalvu0SADzyDfEuFkxmfJpL t0ZmQyzDgHrwgVmf2pdiXn7K7VDqqWvHH9ff5hKWS5sU0cIu5Tvs9hD4RCKR+IXIslHv ZKsUPbb7zkBt8dp20Xan5tJXSfA7X/tCUQQuctL661GzTiko1r5PDHqgbRvuOAH7Pd0W tQ9Q== X-Gm-Message-State: AAQBX9dGnLxoyKGDCKjATzloJrBSkoF5KuMQWiJO9SlJyzCVPtJakb1h D9/uZkDGDPohwz2yX9PHlD4b4Ptq/JyO6ZG7nu+oPmDGnFO+qA== X-Google-Smtp-Source: AKy350a66wBoS6i2YtyRhM5gzilAB69jq7Z3eSm+p1a3JJjdiBxSCbYIlyLQvB08aB/rngAy+XvUUeLFLOyMmAGyvSE= X-Received: by 2002:a67:e019:0:b0:414:4ef3:839 with SMTP id c25-20020a67e019000000b004144ef30839mr19063116vsl.7.1680424434457; Sun, 02 Apr 2023 01:33:54 -0700 (PDT) MIME-Version: 1.0 References: <20230329024259.174803-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230329024259.174803-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Sun, 2 Apr 2023 16:33:43 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Fix ICE && codegen error of scalar move in RV32 system. To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Commit as https://gcc.gnu.org/git/?p=3Dgcc.git;a=3Dcommit;h=3Ddb4f7a9b47d14= 8b5074ac15910124c746fb7a96f with more commit log On Wed, Mar 29, 2023 at 10:43=E2=80=AFAM wrote: > > From: Juzhe-Zhong > > bug.C:144:2: error: unrecognizable insn: > 144 | } > | ^ > (insn 684 683 685 26 (set (reg:SI 513) > (and:SI (const_int 4 [0x4]) > (const_int 1 [0x1]))) "bug.C":115:47 -1 > (nil)) > > > andi a4,a4,1 =3D=3D=3D> sgtu a4,a4,zero > vsetlvi tu vsetvli tu > vlse vlse > > gcc/ChangeLog: > > * config/riscv/riscv-protos.h (gen_avl_for_scalar_move): New func= tion. > * config/riscv/riscv-v.cc (gen_avl_for_scalar_move): New function= . > * config/riscv/vector.md: Fix scalar move bug. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/scalar_move-6.c: Adapt test. > * gcc.target/riscv/rvv/base/scalar_move-9.c: New test. > > --- > gcc/config/riscv/riscv-protos.h | 1 + > gcc/config/riscv/riscv-v.cc | 19 ++++++++++++++ > gcc/config/riscv/vector.md | 8 ++---- > .../gcc.target/riscv/rvv/base/scalar_move-6.c | 8 ------ > .../gcc.target/riscv/rvv/base/scalar_move-9.c | 26 +++++++++++++++++++ > 5 files changed, 48 insertions(+), 14 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9= .c > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-pro= tos.h > index e41f65a0894..4611447ddde 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -205,6 +205,7 @@ enum vlen_enum > }; > bool slide1_sew64_helper (int, machine_mode, machine_mode, > machine_mode, rtx *); > +rtx gen_avl_for_scalar_move (rtx); > } > > /* We classify builtin types into two classes: > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index d7b77fd6123..968db0831f1 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -701,4 +701,23 @@ slide1_sew64_helper (int unspec, machine_mode mode, = machine_mode demote_mode, > return true; > } > > +rtx > +gen_avl_for_scalar_move (rtx avl) > +{ > + if (CONST_INT_P (avl)) > + { > + if (rtx_equal_p (avl, const0_rtx)) > + return const0_rtx; > + else > + return const1_rtx; > + } > + else > + { > + rtx tmp =3D gen_reg_rtx (Pmode); > + emit_insn ( > + gen_rtx_SET (tmp, gen_rtx_fmt_ee (GTU, Pmode, avl, const0_rtx))); > + return tmp; > + } > +} > + > } // namespace riscv_vector > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index 52597750f69..6c8e046bd29 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -1229,9 +1229,7 @@ > else if (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (Pmod= e)) > { > // Case 2: vmv.s.x (TU) =3D=3D> andi vl + vlse.v (TU) in RV= 32 system. > - rtx tmp =3D gen_reg_rtx (Pmode); > - emit_insn (gen_rtx_SET (tmp, gen_rtx_AND (Pmode, operands[= 4], const1_rtx))); > - operands[4] =3D tmp; > + operands[4] =3D riscv_vector::gen_avl_for_scalar_move (oper= ands[4]); > operands[1] =3D CONSTM1_RTX (mode); > } > else > @@ -1292,9 +1290,7 @@ > vlse64.v */ > if (satisfies_constraint_Wb1 (operands[1])) > { > - rtx tmp =3D gen_reg_rtx (Pmode); > - emit_insn (gen_rtx_SET (tmp, gen_rtx_AND (Pmode, operands[4], co= nst1_rtx))); > - operands[4] =3D tmp; > + operands[4] =3D riscv_vector::gen_avl_for_scalar_move (operands[4= ]); > operands[1] =3D CONSTM1_RTX (mode); > } > } > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c b/gc= c/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c > index 268ddd7c116..f27f85cdb58 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c > @@ -37,8 +37,6 @@ void foo2 (void *base, void *out, size_t vl) > /* > ** foo3: > ** ... > -** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1 > -** ... > ** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero > ** ... > ** ret > @@ -54,8 +52,6 @@ void foo3 (void *base, void *out, size_t vl) > /* > ** foo4: > ** ... > -** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1 > -** ... > ** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero > ** ... > ** ret > @@ -137,8 +133,6 @@ void foo9 (void *base, void *out, size_t vl) > /* > ** foo10: > ** ... > -** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1 > -** ... > ** vmv.v.i\tv[0-9]+,\s*-15 > ** ... > */ > @@ -167,8 +161,6 @@ void foo11 (void *base, void *out, size_t vl) > /* > ** foo12: > ** ... > -** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1 > -** ... > ** vmv.v.i\tv[0-9]+,\s*0 > ** ... > ** ret > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gc= c/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c > new file mode 100644 > index 00000000000..80ee1b5f0c9 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c > @@ -0,0 +1,26 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gcv -mabi=3Dilp32d -fno-schedule-insns -fn= o-schedule-insns2 -O3" } */ > + > +#include "riscv_vector.h" > + > +vuint64m2_t f1(vuint64m2_t var_17, uint64_t var_60) > +{ > + vuint64m2_t var_16 =3D __riscv_vmv_s_x_u64m2_tu(var_17,var_60, 0); > + return var_16; > +} > + > +vuint64m2_t f2(vuint64m2_t var_17, uint64_t var_60) > +{ > + vuint64m2_t var_16 =3D __riscv_vmv_s_x_u64m2_tu(var_17,var_60, 4); > + return var_16; > +} > + > +vuint64m2_t f3(vuint64m2_t var_17, uint64_t var_60, size_t vl) > +{ > + vuint64m2_t var_16 =3D __riscv_vmv_s_x_u64m2_tu(var_17,var_60, vl); > + return var_16; > +} > + > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*0,\s*e64,\s*m2,= \s*t[au],\s*m[au]} 1 } } */ > +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m2,= \s*t[au],\s*m[au]} 1 } } */ > +/* { dg-final { scan-assembler-times {sgtu} 1 } } */ > -- > 2.36.3 >