From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe2d.google.com (mail-vs1-xe2d.google.com [IPv6:2607:f8b0:4864:20::e2d]) by sourceware.org (Postfix) with ESMTPS id 444AF385841C for ; Fri, 3 Feb 2023 07:16:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 444AF385841C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe2d.google.com with SMTP id j7so4441587vsl.11 for ; Thu, 02 Feb 2023 23:16:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=shf2Rw4YMM+3qPdAQ2jD+Qayrb8LZAIR1ErIIbbdG+s=; b=hkwNZb2jX2fL80Vsq0mUgSa0z3da82dOTkrUUM5FWuIjzLh6TaBO6cM75pKJaQfxLX 0bPEnKxvjKWqYM1DUCfPjn9cfXcEHNAtxkjvPngviZ2eRt19jcMeOMFZK+Mc10HTvkPy cilOwPaoVt9kA9T6aFr61LU5lVyU8XRb1JsRTSKYWyNynJanpjIGedsFi47fGYMpYLL2 gOzqb3V9FttPeulMl+/FNvRR2jfWRodnquvDaCjAN9AllPmQuSeVnLJjve2f0ootm8ju 4J2Kqw9BUxDkHzKyoESVGgK/J3JBmnDJTcv4et0lEarxt5CaKXMo8DFRdtDEm/+4IBMx jQ0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=shf2Rw4YMM+3qPdAQ2jD+Qayrb8LZAIR1ErIIbbdG+s=; b=l9JvI4FMPMBvPSUwWDBIfBduDvhNHJXiS6dCZbmfFyo6XoVcUZG+946LAcefvDL30Y eSvvIYkF1GUC5QaP0WGwprxbl7JY00V3DBQQCdk80P8PtvBaye7fkAP5zjqczVysXNA4 q/4T3epak7U7eThd1A5ZvreW2T6KAnNqiMWROUTCj03cSQD8rUV74MzB/0qilwx0vK97 LdFV0OkWpagTSgkARMo/2AApwmbJ6s8rEJ/7Afo6sAjVzoiBs544mve8ST6qYh8V0oqr qwmi+Mp+suC3JnkxSB6KQuTZPx6h0iaGrvDsva3Gp2edGVtrnSfK6oBJ9FiMhyzrbKlA 10FQ== X-Gm-Message-State: AO0yUKUENzOpYL4lwlLRBgXq8sVpNfiUSnSMxqqx2TeYiq1T+WNDW4JD pAwueLq+wJA163Lbob/r1bhY1nGShl7M9LSCt2w= X-Google-Smtp-Source: AK7set+G7ZG6Ru2bwxVIgdE2d+5mVsGR+vpF30KYJXP8JE7aVoZDFcGwfShZoNcnu2BVlpCSTZ/vMpN0MZmas0LlSwU= X-Received: by 2002:a67:f14b:0:b0:3ff:eb31:bd5e with SMTP id t11-20020a67f14b000000b003ffeb31bd5emr1472836vsm.84.1675408580294; Thu, 02 Feb 2023 23:16:20 -0800 (PST) MIME-Version: 1.0 References: <20230131220724.19131-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230131220724.19131-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Fri, 3 Feb 2023 15:16:09 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add RVV shift.vx C/C++ API support To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: committed, thanks! On Wed, Feb 1, 2023 at 6:08 AM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/predicates.md (pmode_reg_or_uimm5_operand): New predicate. > * config/riscv/riscv-vector-builtins-bases.cc: New class. > * config/riscv/riscv-vector-builtins-functions.def (vsll): Ditto. > (vsra): Ditto. > (vsrl): Ditto. > * config/riscv/riscv-vector-builtins.cc: Ditto. > * config/riscv/vector.md (@pred__scalar): New pattern. > > --- > gcc/config/riscv/predicates.md | 8 ++++++ > .../riscv/riscv-vector-builtins-bases.cc | 10 ++++++- > .../riscv/riscv-vector-builtins-functions.def | 3 +++ > gcc/config/riscv/riscv-vector-builtins.cc | 13 ++++++++++ > gcc/config/riscv/vector.md | 26 +++++++++++++++++++ > 5 files changed, 59 insertions(+), 1 deletion(-) > > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md > index 57f7ddfbd7d..895831443e1 100644 > --- a/gcc/config/riscv/predicates.md > +++ b/gcc/config/riscv/predicates.md > @@ -301,6 +301,14 @@ > (and (match_code "const_vector") > (match_test "riscv_vector::const_vec_all_same_in_range_p (op, 0, 31)")))) > > +;; pmode_reg_or_uimm5_operand can be used by vsll.vx/vsrl.vx/vsra.vx instructions. > +;; Since it has the same predicate with vector_length_operand which allows register > +;; or immediate (0 ~ 31), we define this predicate same as vector_length_operand here. > +;; We don't use vector_length_operand directly to predicate vsll.vx/vsrl.vx/vsra.vx > +;; since it may be confusing. > +(define_special_predicate "pmode_reg_or_uimm5_operand" > + (match_operand 0 "vector_length_operand")) > + > (define_special_predicate "pmode_reg_or_0_operand" > (ior (match_operand 0 "const_0_operand") > (match_operand 0 "pmode_register_operand"))) > diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc > index f4256fedc5b..00d357a0d36 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc > +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc > @@ -163,7 +163,15 @@ class binop : public function_base > public: > rtx expand (function_expander &e) const override > { > - return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ())); > + switch (e.op_info->op) > + { > + case OP_TYPE_vx: > + return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode ())); > + case OP_TYPE_vv: > + return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ())); > + default: > + gcc_unreachable (); > + } > } > }; > > diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def > index 9f9678ab6dd..b543946c72e 100644 > --- a/gcc/config/riscv/riscv-vector-builtins-functions.def > +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def > @@ -80,5 +80,8 @@ DEF_RVV_FUNCTION (vdiv, binop, full_preds, iu_vvv_ops) > DEF_RVV_FUNCTION (vrem, binop, full_preds, iu_vvv_ops) > DEF_RVV_FUNCTION (vdivu, binop, full_preds, iu_vvv_ops) > DEF_RVV_FUNCTION (vremu, binop, full_preds, iu_vvv_ops) > +DEF_RVV_FUNCTION (vsll, binop, full_preds, iu_shift_vvx_ops) > +DEF_RVV_FUNCTION (vsra, binop, full_preds, iu_shift_vvx_ops) > +DEF_RVV_FUNCTION (vsrl, binop, full_preds, iu_shift_vvx_ops) > > #undef DEF_RVV_FUNCTION > diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc > index 3a6c2c7c6f2..12fea2b3594 100644 > --- a/gcc/config/riscv/riscv-vector-builtins.cc > +++ b/gcc/config/riscv/riscv-vector-builtins.cc > @@ -249,6 +249,11 @@ static CONSTEXPR const rvv_arg_type_info shift_vv_args[] > = {rvv_arg_type_info (RVV_BASE_vector), > rvv_arg_type_info (RVV_BASE_shift_vector), rvv_arg_type_info_end}; > > +/* A list of args for vector_type func (vector_type, size) function. */ > +static CONSTEXPR const rvv_arg_type_info vector_size_args[] > + = {rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info (RVV_BASE_size), > + rvv_arg_type_info_end}; > + > /* A list of none preds that will be registered for intrinsic functions. */ > static CONSTEXPR const predication_type_index none_preds[] > = {PRED_TYPE_none, NUM_PRED_TYPES}; > @@ -405,6 +410,14 @@ static CONSTEXPR const rvv_op_info iu_shift_vvv_ops > rvv_arg_type_info (RVV_BASE_vector), /* Return type */ > shift_vv_args /* Args */}; > > +/* A static operand information for vector_type func (vector_type, size_t) > + * function registration. */ > +static CONSTEXPR const rvv_op_info iu_shift_vvx_ops > + = {iu_ops, /* Types */ > + OP_TYPE_vx, /* Suffix */ > + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ > + vector_size_args /* Args */}; > + > /* A list of all RVV intrinsic functions. */ > static function_group_info function_groups[] = { > #define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) \ > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index e8d75f164e3..36b0e07728c 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -1148,3 +1148,29 @@ > v\t%0,%p1" > [(set_attr "type" "") > (set_attr "mode" "")]) > + > +;; vx instructions patterns. > +;; Note: Unlike vv patterns, we should split them since they are variant. > +;; For vsll.vx/vsra.vx/vsrl.vx the scalar mode should be Pmode wheras the > +;; scalar mode is inner mode of the RVV mode for other vx patterns. > +(define_insn "@pred__scalar" > + [(set (match_operand:VI 0 "register_operand" "=vr, vr") > + (if_then_else:VI > + (unspec: > + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") > + (match_operand 5 "vector_length_operand" " rK, rK") > + (match_operand 6 "const_int_operand" " i, i") > + (match_operand 7 "const_int_operand" " i, i") > + (match_operand 8 "const_int_operand" " i, i") > + (reg:SI VL_REGNUM) > + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (any_shift:VI > + (match_operand:VI 3 "register_operand" " vr, vr") > + (match_operand 4 "pmode_reg_or_uimm5_operand" " r, K")) > + (match_operand:VI 2 "vector_merge_operand" "0vu, 0vu")))] > + "TARGET_VECTOR" > + "@ > + v.vx\t%0,%3,%4%p1 > + v.vi\t%0,%3,%4%p1" > + [(set_attr "type" "vshift") > + (set_attr "mode" "")]) > -- > 2.36.3 >