* [PATCH v1] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch
@ 2024-06-14 7:01 pan2.li
2024-06-14 7:32 ` Kito Cheng
0 siblings, 1 reply; 3+ messages in thread
From: pan2.li @ 2024-06-14 7:01 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
We have vec_extract pattern which takes ZVFHMIN as the mode
iterator of the V mode. Aka VF_ZVFHMIN iterator. But it will
expand to pred_extract_first pattern which takes the ZVFH as the mode
iterator of the V mode. AKa VF. The mismatch will result in one ICE
similar as below:
insn 30 29 31 2 (set (reg:HF 156 [ _2 ])
(unspec:HF [
(vec_select:HF (reg:RVVMF2HF 134 [ _1 ])
(parallel [
(const_int 0 [0])
]))
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)) "compress_run-2.c":22:3 -1
(nil))
during RTL pass: vregs
compress_run-2.c:25:1: internal compiler error: in extract_insn, at
recog.cc:2812
0xb3bc47 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
../../../gcc/gcc/rtl-error.cc:108
0xb3bc69 _fatal_insn_not_found(rtx_def const*, char const*, int, char
const*)
../../../gcc/gcc/rtl-error.cc:116
0xb3a545 extract_insn(rtx_insn*)
../../../gcc/gcc/recog.cc:2812
0x1010e9e instantiate_virtual_regs_in_insn
../../../gcc/gcc/function.cc:1612
0x1010e9e instantiate_virtual_regs
../../../gcc/gcc/function.cc:1995
0x1010e9e execute
../../../gcc/gcc/function.cc:2042
The below test suites are passed for this patch.
1. The rv64gcv fully regression test.
2. The rv64gcv build with glibc.
There may be other similar issue(s) for the mismatch, we will take care
of them by test cases one by one.
PR target/115456
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Leverage V_ZVFH instead of V
which contains the VF_ZVFHMIN for alignment.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr115456-2.c: New test.
* gcc.target/riscv/rvv/base/pr115456-3.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/vector-iterators.md | 4 ++-
.../gcc.target/riscv/rvv/base/pr115456-2.c | 31 +++++++++++++++++++
.../gcc.target/riscv/rvv/base/pr115456-3.c | 31 +++++++++++++++++++
3 files changed, 65 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 47392d0da4c..43137a2a379 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1578,9 +1578,11 @@ (define_mode_iterator VLS_ZVFH [VLSI VLSF])
(define_mode_iterator V [VI VF_ZVFHMIN])
+(define_mode_iterator V_ZVFH [VI VF])
+
(define_mode_iterator V_VLS [V VLS])
-(define_mode_iterator V_VLS_ZVFH [V VLS_ZVFH])
+(define_mode_iterator V_VLS_ZVFH [V_ZVFH VLS_ZVFH])
(define_mode_iterator V_VLSI [VI VLSI])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
new file mode 100644
index 00000000000..453e18b1c79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
@@ -0,0 +1,31 @@
+/* Test there is no ICE when compile. */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mrvv-vector-bits=zvl -mabi=lp64d -O3 -ftree-vectorize" } */
+
+#include <assert.h>
+#include <stdint-gcc.h>
+
+typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
+
+vnx4f __attribute__ ((noinline, noclone))
+test_5 (vnx4f x, vnx4f y)
+{
+ return __builtin_shufflevector (x, y, 1, 3, 6, 7);
+}
+
+int
+main (void)
+{
+ vnx4f test_5_x = {0, 1, 3, 4};
+ vnx4f test_5_y = {4, 5, 6, 7};
+ vnx4f test_5_except = {1, 4, 6, 7};
+ vnx4f test_5_real;
+ test_5_real = test_5 (test_5_x, test_5_y);
+
+ for (int i = 0; i < 4; i++)
+ assert (test_5_real[i] == test_5_except[i]);
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {call\s+__extendhfsf2} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
new file mode 100644
index 00000000000..2c54f1d7538
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize" } */
+
+#include <assert.h>
+#include <stdint-gcc.h>
+
+typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
+
+vnx4f __attribute__ ((noinline, noclone))
+test_5 (vnx4f x, vnx4f y)
+{
+ return __builtin_shufflevector (x, y, 1, 3, 6, 7);
+}
+
+int
+main (void)
+{
+ vnx4f test_5_x = {0, 1, 3, 4};
+ vnx4f test_5_y = {4, 5, 6, 7};
+ vnx4f test_5_except = {1, 4, 6, 7};
+ vnx4f test_5_real;
+ test_5_real = test_5 (test_5_x, test_5_y);
+
+ for (int i = 0; i < 4; i++)
+ assert (test_5_real[i] == test_5_except[i]);
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-not {call\s+__extendhfsf2} } } */
+/* { dg-final { scan-assembler-times {vfmv\.f\.s\s+fa[0-9]+,\s*v[0-9]+} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch
2024-06-14 7:01 [PATCH v1] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch pan2.li
@ 2024-06-14 7:32 ` Kito Cheng
2024-06-14 7:56 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: Kito Cheng @ 2024-06-14 7:32 UTC (permalink / raw)
To: pan2.li; +Cc: gcc-patches, juzhe.zhong, jeffreyalaw, rdapp.gcc
LGTM, thanks :)
On Fri, Jun 14, 2024 at 3:02 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> We have vec_extract pattern which takes ZVFHMIN as the mode
> iterator of the V mode. Aka VF_ZVFHMIN iterator. But it will
> expand to pred_extract_first pattern which takes the ZVFH as the mode
> iterator of the V mode. AKa VF. The mismatch will result in one ICE
> similar as below:
>
> insn 30 29 31 2 (set (reg:HF 156 [ _2 ])
> (unspec:HF [
> (vec_select:HF (reg:RVVMF2HF 134 [ _1 ])
> (parallel [
> (const_int 0 [0])
> ]))
> (reg:SI 67 vtype)
> ] UNSPEC_VPREDICATE)) "compress_run-2.c":22:3 -1
> (nil))
> during RTL pass: vregs
> compress_run-2.c:25:1: internal compiler error: in extract_insn, at
> recog.cc:2812
> 0xb3bc47 _fatal_insn(char const*, rtx_def const*, char const*, int, char
> const*)
> ../../../gcc/gcc/rtl-error.cc:108
> 0xb3bc69 _fatal_insn_not_found(rtx_def const*, char const*, int, char
> const*)
> ../../../gcc/gcc/rtl-error.cc:116
> 0xb3a545 extract_insn(rtx_insn*)
> ../../../gcc/gcc/recog.cc:2812
> 0x1010e9e instantiate_virtual_regs_in_insn
> ../../../gcc/gcc/function.cc:1612
> 0x1010e9e instantiate_virtual_regs
> ../../../gcc/gcc/function.cc:1995
> 0x1010e9e execute
> ../../../gcc/gcc/function.cc:2042
>
> The below test suites are passed for this patch.
> 1. The rv64gcv fully regression test.
> 2. The rv64gcv build with glibc.
>
> There may be other similar issue(s) for the mismatch, we will take care
> of them by test cases one by one.
>
> PR target/115456
>
> gcc/ChangeLog:
>
> * config/riscv/vector-iterators.md: Leverage V_ZVFH instead of V
> which contains the VF_ZVFHMIN for alignment.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr115456-2.c: New test.
> * gcc.target/riscv/rvv/base/pr115456-3.c: New test.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> gcc/config/riscv/vector-iterators.md | 4 ++-
> .../gcc.target/riscv/rvv/base/pr115456-2.c | 31 +++++++++++++++++++
> .../gcc.target/riscv/rvv/base/pr115456-3.c | 31 +++++++++++++++++++
> 3 files changed, 65 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
>
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index 47392d0da4c..43137a2a379 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -1578,9 +1578,11 @@ (define_mode_iterator VLS_ZVFH [VLSI VLSF])
>
> (define_mode_iterator V [VI VF_ZVFHMIN])
>
> +(define_mode_iterator V_ZVFH [VI VF])
> +
> (define_mode_iterator V_VLS [V VLS])
>
> -(define_mode_iterator V_VLS_ZVFH [V VLS_ZVFH])
> +(define_mode_iterator V_VLS_ZVFH [V_ZVFH VLS_ZVFH])
>
> (define_mode_iterator V_VLSI [VI VLSI])
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
> new file mode 100644
> index 00000000000..453e18b1c79
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
> @@ -0,0 +1,31 @@
> +/* Test there is no ICE when compile. */
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfhmin -mrvv-vector-bits=zvl -mabi=lp64d -O3 -ftree-vectorize" } */
> +
> +#include <assert.h>
> +#include <stdint-gcc.h>
> +
> +typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
> +
> +vnx4f __attribute__ ((noinline, noclone))
> +test_5 (vnx4f x, vnx4f y)
> +{
> + return __builtin_shufflevector (x, y, 1, 3, 6, 7);
> +}
> +
> +int
> +main (void)
> +{
> + vnx4f test_5_x = {0, 1, 3, 4};
> + vnx4f test_5_y = {4, 5, 6, 7};
> + vnx4f test_5_except = {1, 4, 6, 7};
> + vnx4f test_5_real;
> + test_5_real = test_5 (test_5_x, test_5_y);
> +
> + for (int i = 0; i < 4; i++)
> + assert (test_5_real[i] == test_5_except[i]);
> +
> + return 0;
> +}
> +
> +/* { dg-final { scan-assembler-times {call\s+__extendhfsf2} 8 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
> new file mode 100644
> index 00000000000..2c54f1d7538
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
> @@ -0,0 +1,31 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize" } */
> +
> +#include <assert.h>
> +#include <stdint-gcc.h>
> +
> +typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
> +
> +vnx4f __attribute__ ((noinline, noclone))
> +test_5 (vnx4f x, vnx4f y)
> +{
> + return __builtin_shufflevector (x, y, 1, 3, 6, 7);
> +}
> +
> +int
> +main (void)
> +{
> + vnx4f test_5_x = {0, 1, 3, 4};
> + vnx4f test_5_y = {4, 5, 6, 7};
> + vnx4f test_5_except = {1, 4, 6, 7};
> + vnx4f test_5_real;
> + test_5_real = test_5 (test_5_x, test_5_y);
> +
> + for (int i = 0; i < 4; i++)
> + assert (test_5_real[i] == test_5_except[i]);
> +
> + return 0;
> +}
> +
> +/* { dg-final { scan-assembler-not {call\s+__extendhfsf2} } } */
> +/* { dg-final { scan-assembler-times {vfmv\.f\.s\s+fa[0-9]+,\s*v[0-9]+} 4 } } */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH v1] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch
2024-06-14 7:32 ` Kito Cheng
@ 2024-06-14 7:56 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2024-06-14 7:56 UTC (permalink / raw)
To: Kito Cheng; +Cc: gcc-patches, juzhe.zhong, jeffreyalaw, rdapp.gcc
Committed, thanks Kito.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Friday, June 14, 2024 3:33 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; jeffreyalaw@gmail.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH v1] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch
LGTM, thanks :)
On Fri, Jun 14, 2024 at 3:02 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> We have vec_extract pattern which takes ZVFHMIN as the mode
> iterator of the V mode. Aka VF_ZVFHMIN iterator. But it will
> expand to pred_extract_first pattern which takes the ZVFH as the mode
> iterator of the V mode. AKa VF. The mismatch will result in one ICE
> similar as below:
>
> insn 30 29 31 2 (set (reg:HF 156 [ _2 ])
> (unspec:HF [
> (vec_select:HF (reg:RVVMF2HF 134 [ _1 ])
> (parallel [
> (const_int 0 [0])
> ]))
> (reg:SI 67 vtype)
> ] UNSPEC_VPREDICATE)) "compress_run-2.c":22:3 -1
> (nil))
> during RTL pass: vregs
> compress_run-2.c:25:1: internal compiler error: in extract_insn, at
> recog.cc:2812
> 0xb3bc47 _fatal_insn(char const*, rtx_def const*, char const*, int, char
> const*)
> ../../../gcc/gcc/rtl-error.cc:108
> 0xb3bc69 _fatal_insn_not_found(rtx_def const*, char const*, int, char
> const*)
> ../../../gcc/gcc/rtl-error.cc:116
> 0xb3a545 extract_insn(rtx_insn*)
> ../../../gcc/gcc/recog.cc:2812
> 0x1010e9e instantiate_virtual_regs_in_insn
> ../../../gcc/gcc/function.cc:1612
> 0x1010e9e instantiate_virtual_regs
> ../../../gcc/gcc/function.cc:1995
> 0x1010e9e execute
> ../../../gcc/gcc/function.cc:2042
>
> The below test suites are passed for this patch.
> 1. The rv64gcv fully regression test.
> 2. The rv64gcv build with glibc.
>
> There may be other similar issue(s) for the mismatch, we will take care
> of them by test cases one by one.
>
> PR target/115456
>
> gcc/ChangeLog:
>
> * config/riscv/vector-iterators.md: Leverage V_ZVFH instead of V
> which contains the VF_ZVFHMIN for alignment.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr115456-2.c: New test.
> * gcc.target/riscv/rvv/base/pr115456-3.c: New test.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> gcc/config/riscv/vector-iterators.md | 4 ++-
> .../gcc.target/riscv/rvv/base/pr115456-2.c | 31 +++++++++++++++++++
> .../gcc.target/riscv/rvv/base/pr115456-3.c | 31 +++++++++++++++++++
> 3 files changed, 65 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
>
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index 47392d0da4c..43137a2a379 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -1578,9 +1578,11 @@ (define_mode_iterator VLS_ZVFH [VLSI VLSF])
>
> (define_mode_iterator V [VI VF_ZVFHMIN])
>
> +(define_mode_iterator V_ZVFH [VI VF])
> +
> (define_mode_iterator V_VLS [V VLS])
>
> -(define_mode_iterator V_VLS_ZVFH [V VLS_ZVFH])
> +(define_mode_iterator V_VLS_ZVFH [V_ZVFH VLS_ZVFH])
>
> (define_mode_iterator V_VLSI [VI VLSI])
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
> new file mode 100644
> index 00000000000..453e18b1c79
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
> @@ -0,0 +1,31 @@
> +/* Test there is no ICE when compile. */
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfhmin -mrvv-vector-bits=zvl -mabi=lp64d -O3 -ftree-vectorize" } */
> +
> +#include <assert.h>
> +#include <stdint-gcc.h>
> +
> +typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
> +
> +vnx4f __attribute__ ((noinline, noclone))
> +test_5 (vnx4f x, vnx4f y)
> +{
> + return __builtin_shufflevector (x, y, 1, 3, 6, 7);
> +}
> +
> +int
> +main (void)
> +{
> + vnx4f test_5_x = {0, 1, 3, 4};
> + vnx4f test_5_y = {4, 5, 6, 7};
> + vnx4f test_5_except = {1, 4, 6, 7};
> + vnx4f test_5_real;
> + test_5_real = test_5 (test_5_x, test_5_y);
> +
> + for (int i = 0; i < 4; i++)
> + assert (test_5_real[i] == test_5_except[i]);
> +
> + return 0;
> +}
> +
> +/* { dg-final { scan-assembler-times {call\s+__extendhfsf2} 8 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
> new file mode 100644
> index 00000000000..2c54f1d7538
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
> @@ -0,0 +1,31 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize" } */
> +
> +#include <assert.h>
> +#include <stdint-gcc.h>
> +
> +typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
> +
> +vnx4f __attribute__ ((noinline, noclone))
> +test_5 (vnx4f x, vnx4f y)
> +{
> + return __builtin_shufflevector (x, y, 1, 3, 6, 7);
> +}
> +
> +int
> +main (void)
> +{
> + vnx4f test_5_x = {0, 1, 3, 4};
> + vnx4f test_5_y = {4, 5, 6, 7};
> + vnx4f test_5_except = {1, 4, 6, 7};
> + vnx4f test_5_real;
> + test_5_real = test_5 (test_5_x, test_5_y);
> +
> + for (int i = 0; i < 4; i++)
> + assert (test_5_real[i] == test_5_except[i]);
> +
> + return 0;
> +}
> +
> +/* { dg-final { scan-assembler-not {call\s+__extendhfsf2} } } */
> +/* { dg-final { scan-assembler-times {vfmv\.f\.s\s+fa[0-9]+,\s*v[0-9]+} 4 } } */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-06-14 7:01 [PATCH v1] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch pan2.li
2024-06-14 7:32 ` Kito Cheng
2024-06-14 7:56 ` Li, Pan2
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