From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id 6BDCC382B5FF for ; Tue, 7 Jun 2022 10:28:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6BDCC382B5FF Received: by mail-ej1-x62f.google.com with SMTP id gl15so20386637ejb.4 for ; Tue, 07 Jun 2022 03:28:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=A/zelc1ag0yqvug7bDoE3Gzbg57zmn4VPcTB1HPLP78=; b=3xJ6vpR3n8euLNzBGt9H+qXD0WbvzMq8tK8yB+xZhGvPkgfhe37W5MjEI66MKMAFAk FbdwCZj5iz/Aedk062cwdBm5M0dz7eKAHrcFOGUDCVwmyoy5gW4ltKQrpQeQVTlWGjID FWCLyzQ+QG1Ux33erf3O8yLpY/+R1LPRBqNI4QReKJCXJVfvjII8DQIYnsItcJKuz1J3 l0b01t75IC2C3v6+i5jLnh/nHWMT7b4xMU/y4qswsQpeVwdEXGoOkClTD4DTDrDb/+BH R2AFExpoSEUvJuUWEqKMvMXqCZA9Y07Ea9cfrMd4R+sRssAvfR6TYGYBllRMrcQKw2qz fFnw== X-Gm-Message-State: AOAM531fOtZgFORYSFnqxLlS6Y/kHovw/CeKUotdGq8p2fqnlp/cC708 l18YwB8uv9YCVC+GyuClYIXJRbUReZ5ZxsYnay2dg3Zv X-Google-Smtp-Source: ABdhPJxUYUEkT1C3oyKVe4eD8sxxOivDbRRy5Wm74c2wdn+RQs5V4CdraGgUzkzz3xTOqj7sIabgWrXHvYUg9Jz6gWE= X-Received: by 2002:a17:907:a422:b0:705:e944:fd3e with SMTP id sg34-20020a170907a42200b00705e944fd3emr25078588ejc.309.1654597679905; Tue, 07 Jun 2022 03:27:59 -0700 (PDT) MIME-Version: 1.0 References: <20220529215127.482180-1-philipp.tomsich@vrull.eu> In-Reply-To: From: Kito Cheng Date: Tue, 7 Jun 2022 18:27:47 +0800 Message-ID: Subject: Re: [PATCH v2] RISC-V: bitmanip: improve constant-loading for (1ULL << 31) in DImode To: Philipp Tomsich Cc: Vineet Gupta , GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Jun 2022 10:28:03 -0000 > OK for backport? OK, it seems no issue after a week :) > > On Thu, 2 Jun 2022 at 21:23, Philipp Tomsich wrote: > > > > Thanks, applied to trunk! > > > > On Thu, 2 Jun 2022 at 15:17, Kito Cheng wrote: > > > > > > LGTM > > > > > > On Mon, May 30, 2022 at 5:52 AM Philipp Tomsich > > > wrote: > > > > > > > > The SINGLE_BIT_MASK_OPERAND() is overly restrictive, triggering for > > > > bits above 31 only (to side-step any issues with the negative SImode > > > > value 0x80000000/(-1ull << 31)/(1 << 31)). This moves the special > > > > handling of this SImode value (i.e. the check for (-1ull << 31) to > > > > riscv.cc and relaxes the SINGLE_BIT_MASK_OPERAND() test. > > > > > > > > With this, the code-generation for loading (1ULL << 31) from: > > > > li a0,1 > > > > slli a0,a0,31 > > > > to: > > > > bseti a0,zero,31 > > > > > > > > gcc/ChangeLog: > > > > > > > > * config/riscv/riscv.cc (riscv_build_integer_1): Rewrite value as > > > > (-1 << 31) for the single-bit case, when operating on (1 << 31) > > > > in SImode. > > > > * gcc/config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): Allow for > > > > any single-bit value, moving the special case for (1 << 31) to > > > > riscv_build_integer_1 (in riscv.c). > > > > > > > > Signed-off-by: Philipp Tomsich > > > > > > > > --- > > > > > > > > Changes in v2: > > > > - Use HOST_WIDE_INT_1U/HOST_WIDE_INT_M1U instead of constants. > > > > - Fix some typos in the comment above the rewrite of the value. > > > > - Update the comment to clarify that we expect a LUI to be emitted for > > > > the SImode case (i.e. sign-extended for RV64) of (1 << 31). > > > > > > > > gcc/config/riscv/riscv.cc | 9 +++++++++ > > > > gcc/config/riscv/riscv.h | 11 ++++------- > > > > 2 files changed, 13 insertions(+), 7 deletions(-) > > > > > > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > > > index f83dc796d88..2e83ca07394 100644 > > > > --- a/gcc/config/riscv/riscv.cc > > > > +++ b/gcc/config/riscv/riscv.cc > > > > @@ -420,6 +420,15 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], > > > > /* Simply BSETI. */ > > > > codes[0].code = UNKNOWN; > > > > codes[0].value = value; > > > > + > > > > + /* RISC-V sign-extends all 32bit values that live in a 32bit > > > > + register. To avoid paradoxes, we thus need to use the > > > > + sign-extended (negative) representation (-1 << 31) for the > > > > + value, if we want to build (1 << 31) in SImode. This will > > > > + then expand to an LUI instruction. */ > > > > + if (mode == SImode && value == (HOST_WIDE_INT_1U << 31)) > > > > + codes[0].value = (HOST_WIDE_INT_M1U << 31); > > > > + > > > > return 1; > > > > } > > > > > > > > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > > > > index 5083a1c24b0..6f7f4d3fbdc 100644 > > > > --- a/gcc/config/riscv/riscv.h > > > > +++ b/gcc/config/riscv/riscv.h > > > > @@ -528,13 +528,10 @@ enum reg_class > > > > (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \ > > > > || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0) > > > > > > > > -/* If this is a single bit mask, then we can load it with bseti. But this > > > > - is not useful for any of the low 31 bits because we can use addi or lui > > > > - to load them. It is wrong for loading SImode 0x80000000 on rv64 because it > > > > - needs to be sign-extended. So we restrict this to the upper 32-bits > > > > - only. */ > > > > -#define SINGLE_BIT_MASK_OPERAND(VALUE) \ > > > > - (pow2p_hwi (VALUE) && (ctz_hwi (VALUE) >= 32)) > > > > +/* If this is a single bit mask, then we can load it with bseti. Special > > > > + handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */ > > > > +#define SINGLE_BIT_MASK_OPERAND(VALUE) \ > > > > + (pow2p_hwi (VALUE)) > > > > > > > > /* Stack layout; function entry, exit and calling. */ > > > > > > > > -- > > > > 2.34.1 > > > >