From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by sourceware.org (Postfix) with ESMTPS id 4AA3E3857C4E for ; Thu, 23 Jun 2022 16:44:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4AA3E3857C4E Received: by mail-ed1-x52a.google.com with SMTP id cf14so19616818edb.8 for ; Thu, 23 Jun 2022 09:44:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ZpI7hz/zESBiRXzFmH2Zly2yCNkX1iECK66StHz6rjM=; b=itDwUFP+5X6GW3vU7L59nRDQNgmRrdD/dvurs6CWLNqqNewbq3b6uF1XOoBPWMSspf J5DgVdrg/Z+a9MPXTZuX1tybOlnKdfi92Kt8K9IHA64Tu/rdP8wKR6rvgSDsDaDvcebe hZ2yRL+mXKT+phg8nVttOeKBucJRdS0k7emsUEXu+gFzc3zbrUrTUrl/ZHx5zi9uOwts VhufdZmRC0o30Tds0149lTifKQrgitgFmq5i97cdGKxcmeYfpWRvyKN8sKummeEkMiOh MVysbRyPjY5KUVRothAu319c9S/PMBEIGom2pY+O9kVwidXliGwOqCpJAGzZXxvB41bj B73A== X-Gm-Message-State: AJIora8xY6hifH+qco2C/MOqhLj4EI1p9OQZCrDlx4XCyPpCT2fZ0lQn NAFHcokFAh1MXJD4QY5iJxncl8yUh6E1gwXhYus= X-Google-Smtp-Source: AGRyM1vbce2N56qIP2dK/dZkcnzbROr3vkv/TgYu2UMDYPId3/oL9tcb2mo7TymsekLywKOAfZeaOVTtRf//2e1UXfw= X-Received: by 2002:aa7:d795:0:b0:435:7fc8:2d1b with SMTP id s21-20020aa7d795000000b004357fc82d1bmr12053383edq.201.1656002688740; Thu, 23 Jun 2022 09:44:48 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Kito Cheng Date: Fri, 24 Jun 2022 00:44:36 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Split unordered FP comparisons into individual RTL insns To: "Maciej W. Rozycki" Cc: GCC Patches , Andrew Waterman Content-Type: multipart/mixed; boundary="000000000000029a6605e2202c94" X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Jun 2022 16:44:52 -0000 --000000000000029a6605e2202c94 Content-Type: text/plain; charset="UTF-8" Hi Maciej: Thanks for detail analysis and performance number report, I am concern about this patch might let compiler schedule the fsflags/frflags with other floating point instructions, and the major issue is we didn't model fflags right in GCC as you mentioned in the first email. So I think we should model this right before we split that, I guess that would be a bunch of work: 1. Add fflags to the hard register list. 2. Add (clobber (reg fflags)) or (set (reg fflags) (fpop (operands...))) to those floating point operations which might change fflags 3. Rewrite riscv_frflags and riscv_fsflags pattern by right RTL pattern: (set (reg) (reg fflags)) and (set (reg fflags) (reg)). 4. Then split *f_quiet4_default and *f_quiet4_snan pattern. However I am not sure about the code gen impact of 2, especially the impact to the combine pass, not sure if you are interested to give a try? And, I did some hack for part of this approach (1+3+4) got following result for "__builtin_isless (x, y) + __builtin_isless (x, z)": fltlt: frflags a4 # 8 [c=4 l=4] riscv_frflags flt.d a5,fa0,fa1 # 14 [c=4 l=4] *cstoredfdi4 flt.d a0,fa0,fa2 # 17 [c=4 l=4] *cstoredfdi4 fsflags a4 # 18 [c=4 l=4] riscv_fsflags add a0,a0,a5 # 30 [c=4 l=4] adddi3/0 ret # 40 [c=0 l=4] simple_return Verbose version: fltlt: #(insn 8 5 9 (set (reg:SI 14 a4 [88]) # (reg:SI 66 fflags)) "x.c":5:10 258 {riscv_frflags} # (expr_list:REG_DEAD (reg:SI 66 fflags) # (nil))) frflags a4 # 8 [c=4 l=4] riscv_frflags #(insn 14 11 15 (parallel [ # (set (reg:DI 15 a5 [90]) # (lt:DI (reg/v:DF 42 fa0 [orig:81 x ] [81]) # (reg:DF 43 fa1 [101]))) # (clobber:SI (reg:SI 66 fflags)) # ]) "x.c":5:10 197 {*cstoredfdi4} # (expr_list:REG_DEAD (reg:DF 43 fa1 [101]) # (expr_list:REG_UNUSED (reg:SI 66 fflags) # (nil)))) flt.d a5,fa0,fa1 # 14 [c=4 l=4] *cstoredfdi4 #(insn 17 15 18 (parallel [ # (set (reg:DI 10 a0 [94]) # (lt:DI (reg/v:DF 42 fa0 [orig:81 x ] [81]) # (reg:DF 44 fa2 [102]))) # (clobber:SI (reg:SI 66 fflags)) # ]) "x.c":5:36 197 {*cstoredfdi4} # (expr_list:REG_DEAD (reg:DF 44 fa2 [102]) # (expr_list:REG_DEAD (reg/v:DF 42 fa0 [orig:81 x ] [81]) # (expr_list:REG_UNUSED (reg:SI 66 fflags) # (nil))))) flt.d a0,fa0,fa2 # 17 [c=4 l=4] *cstoredfdi4 #(insn 18 17 19 (set (reg:SI 66 fflags) # (reg:SI 14 a4 [88])) "x.c":5:36 259 {riscv_fsflags} # (expr_list:REG_DEAD (reg:SI 14 a4 [88]) # (nil))) fsflags a4 # 18 [c=4 l=4] riscv_fsflags #(insn 30 25 31 (set (reg/i:DI 10 a0) # (plus:DI (reg:DI 10 a0 [94]) # (reg:DI 15 a5 [90]))) "x.c":6:1 4 {adddi3} # (expr_list:REG_DEAD (reg:DI 15 a5 [90]) # (nil))) add a0,a0,a5 # 30 [c=4 l=4] adddi3/0 #(jump_insn 40 39 41 (simple_return) "x.c":6:1 244 {simple_return} # (nil) # -> simple_return) ret # 40 [c=0 l=4] simple_return ---- But this hack add an extra use of fflags to prevent FFLAGS getting CSEed, patch attached. --000000000000029a6605e2202c94 Content-Type: text/x-patch; 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