From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x92e.google.com (mail-ua1-x92e.google.com [IPv6:2607:f8b0:4864:20::92e]) by sourceware.org (Postfix) with ESMTPS id E44823858D33 for ; Wed, 19 Apr 2023 15:19:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E44823858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ua1-x92e.google.com with SMTP id v18so11809388uak.8 for ; Wed, 19 Apr 2023 08:19:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681917553; x=1684509553; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=m6NvRoVI5o+rfQeI8op+vhLgDrRedFjnSuoeyBHebos=; b=GpKn8V3BE/iuOmyElbA9qnNBqs337zQ4ymRBBLUQdKuDjeb85qOPLQWwMi3X+CaTH9 teJ1rtcqNZ1JB1L8/Ds7gFKQEVH/tQPwdEUdziBhglaFz4DgMSwNJNZ/S/F10ev0gARk FdVSvB0cSXld65tl+WlizsuGzjwliQIO+WFbdVhMHlrqMCrjMM2IhYdeaf2Z5UUqcblr l1M5ovDy+cmBWaLT50jNMmO0X0X939PaDDBBIxxqZnUHj0CZpsAWZINFglGG2kHnWVG0 F9SFEcqacwmq2yrBw+tXd+E9EFx7t1/wNUS4PLAqq9Zr0J1oMsLQ02+Cur8o0v8Wp5Jy Rpcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681917553; x=1684509553; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m6NvRoVI5o+rfQeI8op+vhLgDrRedFjnSuoeyBHebos=; b=higDCxtKPKI/OMRFF3U42kzbX5MgNjZS0YARAVdIfU0bRGnJooOORGJtqTvKdFT1eS zYP8cbrTl+IDKdykGSajGBjxw+/bG3us4tIPHdZTgE9VfT0NUQQf8Ch4mtMeQcXmlPjt n4G6USpDPmSwp9XrFdviEyXjdUBNvb6UQY5UoRYL9k42EMVLZPJq1X1hE1+vX8E2GXGZ i3kVR+o3nm11mPD/gm32zvpyJB4pZyIpcevga0eIUZYgawwZvasX+PEFI75QlW5L6FFb E7zw10KxmB0Ofw0VyxqqhZUtBSsQGwYaJwzSfs74dg4UMimw9mxT0xM1rZwXpkSHSx6P rEYA== X-Gm-Message-State: AAQBX9c7BFv/wygwV9zPljEdseBKC9C9MAS5xCLXgTLhj7bC4nvAKCKx uoYXHcvgN7X/67dWvu4tEIzp/36ygx45EezeOr4= X-Google-Smtp-Source: AKy350ZuCtKP2FyfjESORirXoYylGQYZLbSJyv5orzQv3M30r1QwmjbFUcnaEQvQzuhMxy4dGTMqSFlLycOJXO7oIf8= X-Received: by 2002:a1f:bdcc:0:b0:440:94d:a57a with SMTP id n195-20020a1fbdcc000000b00440094da57amr235514vkf.6.1681917552810; Wed, 19 Apr 2023 08:19:12 -0700 (PDT) MIME-Version: 1.0 References: <20230417145025.2291874-1-pan2.li@intel.com> <20230419091820.3729443-1-pan2.li@intel.com> In-Reply-To: <20230419091820.3729443-1-pan2.li@intel.com> From: Kito Cheng Date: Wed, 19 Apr 2023 23:19:01 +0800 Message-ID: Subject: Re: [PATCH v3] RISC-V: Align IOR optimization MODE_CLASS condition to AND. To: pan2.li@intel.com Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, kito.cheng@sifive.com, rguenther@suse.de, richard.sandiford@arm.com, yanzhang.wang@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Committed, thanks :) On Wed, Apr 19, 2023 at 5:19=E2=80=AFPM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch aligned the MODE_CLASS condition of the IOR to the AND. Then > more MODE_CLASS besides SCALAR_INT can able to perform the optimization > A | (~A) -> -1 similar to AND operator. For example as below sample code. > > vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t vl) > { > return __riscv_vmorn_mm_b32(v1, v1, vl); > } > > Before this patch: > vsetvli a5,zero,e8,mf4,ta,ma > vlm.v v24,0(a1) > vsetvli zero,a2,e8,mf4,ta,ma > vmorn.mm v24,v24,v24 > vsetvli a5,zero,e8,mf4,ta,ma > vsm.v v24,0(a0) > ret > > After this patch: > vsetvli zero,a2,e8,mf4,ta,ma > vmset.m v24 > vsetvli a5,zero,e8,mf4,ta,ma > vsm.v v24,0(a0) > ret > > Or in RTL's perspective, > from: > (ior:VNx2BI (reg/v:VNx2BI 137 [ v1 ]) (not:VNx2BI (reg/v:VNx2BI 137 [ v1 = ]))) > to: > (const_vector:VNx2BI repeat [ (const_int 1 [0x1]) ]) > > The similar optimization like VMANDN has enabled already. There should > be no difference execpt the operator when compare the VMORN and VMANDN > for such kind of optimization. The patch aligns the IOR MODE_CLASS condit= ion > of the simplification to the AND operator. > > gcc/ChangeLog: > > * simplify-rtx.cc (simplify_context::simplify_binary_operation_1)= : > Align IOR (A | (~A) -> -1) optimization MODE_CLASS condition to= AND. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Update check > condition. > * gcc.target/riscv/simplify_ior_optimization.c: New test. > > Signed-off-by: Pan Li > --- > gcc/simplify-rtx.cc | 4 +- > .../riscv/rvv/base/mask_insn_shortcut.c | 3 +- > .../riscv/simplify_ior_optimization.c | 50 +++++++++++++++++++ > 3 files changed, 53 insertions(+), 4 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/simplify_ior_optimizat= ion.c > > diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc > index c57ff3320ee..d4aeebc7a5f 100644 > --- a/gcc/simplify-rtx.cc > +++ b/gcc/simplify-rtx.cc > @@ -3370,8 +3370,8 @@ simplify_context::simplify_binary_operation_1 (rtx_= code code, > if (((GET_CODE (op0) =3D=3D NOT && rtx_equal_p (XEXP (op0, 0), op1= )) > || (GET_CODE (op1) =3D=3D NOT && rtx_equal_p (XEXP (op1, 0), o= p0))) > && ! side_effects_p (op0) > - && SCALAR_INT_MODE_P (mode)) > - return constm1_rtx; > + && GET_MODE_CLASS (mode) !=3D MODE_CC) > + return CONSTM1_RTX (mode); > > /* (ior A C) is C if all bits of A that might be nonzero are on in= C. */ > if (CONST_INT_P (op1) > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c= b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c > index 83cc4a1b5a5..57d0241675a 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c > @@ -233,9 +233,8 @@ vbool64_t test_shortcut_for_riscv_vmxnor_case_6(vbool= 64_t v1, size_t vl) { > /* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+} } } = */ > /* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+} } } *= / > /* { dg-final { scan-assembler-not {vmnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } = */ > -/* { dg-final { scan-assembler-times {vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*= v[0-9]+} 7 } } */ > /* { dg-final { scan-assembler-not {vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+} } }= */ > /* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 14 } } */ > -/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 7 } } */ > +/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 14 } } */ > /* { dg-final { scan-assembler-times {vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 14 }= } */ > /* { dg-final { scan-assembler-times {vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 14 = } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c b= /gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c > new file mode 100644 > index 00000000000..ec3bd0baf03 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c > @@ -0,0 +1,50 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -O2" } */ > + > +#include > + > +uint8_t test_simplify_ior_scalar_case_0 (uint8_t a) > +{ > + return a | ~a; > +} > + > +uint16_t test_simplify_ior_scalar_case_1 (uint16_t a) > +{ > + return a | ~a; > +} > + > +uint32_t test_simplify_ior_scalar_case_2 (uint32_t a) > +{ > + return a | ~a; > +} > + > +uint64_t test_simplify_ior_scalar_case_3 (uint64_t a) > +{ > + return a | ~a; > +} > + > +int8_t test_simplify_ior_scalar_case_4 (int8_t a) > +{ > + return a | ~a; > +} > + > +int16_t test_simplify_ior_scalar_case_5 (int16_t a) > +{ > + return a | ~a; > +} > + > +int32_t test_simplify_ior_scalar_case_6 (int32_t a) > +{ > + return a | ~a; > +} > + > +int64_t test_simplify_ior_scalar_case_7 (int64_t a) > +{ > + return a | ~a; > +} > + > +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*-1} 6 } } */ > +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*255} 1 } } */ > +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*65536} 1 } } */ > +/* { dg-final { scan-assembler-not {or\s+a[0-9]+} } } */ > +/* { dg-final { scan-assembler-not {not\s+a[0-9]+} } } */ > -- > 2.34.1 >