From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe2e.google.com (mail-vs1-xe2e.google.com [IPv6:2607:f8b0:4864:20::e2e]) by sourceware.org (Postfix) with ESMTPS id 67DF33858D3C for ; Mon, 4 Sep 2023 06:45:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 67DF33858D3C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-vs1-xe2e.google.com with SMTP id ada2fe7eead31-44e8984b724so713950137.1 for ; Sun, 03 Sep 2023 23:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693809934; x=1694414734; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=LW2wIVv+plavRvAfoLxvuzQICU3kb5E38EMYTGOfDOA=; b=etEmEWyvMw8JXWJwnqLedv5DjSgLBAss5EZwkbnQL4aUXSxgWPUyxa7qKDpUTZkiN9 TjZZAaCDZ3e+ysoOqPwPdJCJW4UWHo41pD4yH26bAFbYkMf2Li8u3535hUVo+9paM2w0 o+ok2b/bl4kybSGgNC1kqtoXDnCyTwsQgb2bEdiUWxZMLxtK6EGzyx1FgAlZr0mQDK+0 yn+weczOCkHPOi7CHdkWTO4e06geVMefjZzDqN7Wbqb1WoONbHgKe9tvGJhvn5SDnRMA igmRcrcQxvn0mSKoRt1OrwhfJDNl+D4rH4wa8U9sjyky+QuAJY4pATsgBGdriGbkd/1J 9ANA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693809934; x=1694414734; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LW2wIVv+plavRvAfoLxvuzQICU3kb5E38EMYTGOfDOA=; b=Jpj2l7fuLVSj2o7Jz8PjuI0wjxKjEdpIpW5eM8hOWa+vda2Ep3UHrhpiS6TBV2jCA4 bFW+1LchF1A+tC8I166pgeCSHjDzvTOb1OWk0TswSLdvYo+V8JeVkw+wmVit32b8CFjc 0cV8DcwoS1JI9YXTgPVOkC1zrUeVW2x9H9sjEz5aKQluM0SWrxslaIVgeSJHnIedVqv7 PAgHj5XivhIbcBCr4d6a2DP4HsXBOahq7I8TR5apOz5DTCx7q8JGoZ4FXD7URt03jctY hyrd8LZOKYXEbMnvoxONg5dKOcgrb66h2HQGA2jKMkB//KhrKi77lBan71Z8Xy1bMC5H 3ceg== X-Gm-Message-State: AOJu0YwONxgH4AP6mr8rPFnFd519vyGkBfE8oY2y7NYTvisM7Jgto83c HNv6ejSlZV62V4YYbaHV4n4wAxRtBUIPpn+mxNQ= X-Google-Smtp-Source: AGHT+IG0DHX8Cod8/aIKrbOryRzVhQLzauAULMOvJj+BzN1rTpdjKDzlotXn9jlq1Czw7/zKr2lsUdCO/MSddNT8+xs= X-Received: by 2002:a05:6102:442a:b0:44d:3b54:c81b with SMTP id df42-20020a056102442a00b0044d3b54c81bmr8055480vsb.12.1693809934611; Sun, 03 Sep 2023 23:45:34 -0700 (PDT) MIME-Version: 1.0 References: <3cc5403de383d7c8cfd1769948c2bcf9d54b97f9.1693786829.git.research_trasio@irq.a4lg.com> In-Reply-To: <3cc5403de383d7c8cfd1769948c2bcf9d54b97f9.1693786829.git.research_trasio@irq.a4lg.com> From: Kito Cheng Date: Mon, 4 Sep 2023 14:45:23 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Fix Zicond ICE on large constants To: Tsukasa OI Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law , gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Maybe move the check logic a bit forward? My thought is the logic is already specialized into a few catalogs, (imm, imm), (imm, reg), (reg, reg)... and the logic you put is already in (imm, reg), but it should really move into (reg, reg) case IMO? and move that forward we could prevent add too much logic to redirect the case. diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 2db9c81ac8b..c84509c393b 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3892,6 +3892,12 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) op1 =3D XEXP (op, 1); } + /* CONS might not fit into a signed 12 bit immediate suitable + for an addi instruction. If that's the case, force it into + a register. */ + if (CONST_INT_P (cons) && !SMALL_OPERAND (INTVAL (cons))) + cons =3D force_reg (mode, cons); + /* 0, reg or 0, imm */ if (cons =3D=3D CONST0_RTX (mode) && (REG_P (alt) On Mon, Sep 4, 2023 at 8:21=E2=80=AFAM Tsukasa OI via Gcc-patches wrote: > > From: Tsukasa OI > > Large constant cons and/or alt will trigger ICEs building GCC target > libraries (libgomp and libatomic) when the 'Zicond' extension is enabled. > > For instance, zicond-ice-2.c (new test case in this commit) will cause > an ICE when SOME_NUMBER is 0x1000 or larger. While opposite numbers > corresponding cons/alt (two temp2 variables) are checked, cons/alt > themselves are not checked and causing 2 ICEs building > GCC target libraries as of this writing: > > 1. gcc/libatomic/config/posix/lock.c > 2. gcc/libgomp/fortran.c > > Coercing a large value into a register will fix the issue. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_expand_conditional_move): Force > large constant cons/alt into a register. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/zicond-ice-2.c: New test. This is based on > an ICE at libat_lock_n func on gcc/libatomic/config/posix/lock.c > but heavily minimized. > --- > gcc/config/riscv/riscv.cc | 16 ++++++++++------ > gcc/testsuite/gcc.target/riscv/zicond-ice-2.c | 11 +++++++++++ > 2 files changed, 21 insertions(+), 6 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ice-2.c > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 8d8f7b4f16ed..cfaa4b6a7720 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -3940,11 +3940,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, = rtx cons, rtx alt) > rtx temp1 =3D gen_reg_rtx (mode); > rtx temp2 =3D gen_int_mode (-1 * INTVAL (cons), mode); > > - /* TEMP2 might not fit into a signed 12 bit immediate suitable > - for an addi instruction. If that's the case, force it into > - a register. */ > + /* TEMP2 and/or CONS might not fit into a signed 12 bit immedia= te > + suitable for an addi instruction. If that's the case, force= it > + into a register. */ > if (!SMALL_OPERAND (INTVAL (temp2))) > temp2 =3D force_reg (mode, temp2); > + if (!SMALL_OPERAND (INTVAL (cons))) > + cons =3D force_reg (mode, cons); > > riscv_emit_binary (PLUS, temp1, alt, temp2); > emit_insn (gen_rtx_SET (dest, > @@ -3986,11 +3988,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, = rtx cons, rtx alt) > rtx temp1 =3D gen_reg_rtx (mode); > rtx temp2 =3D gen_int_mode (-1 * INTVAL (alt), mode); > > - /* TEMP2 might not fit into a signed 12 bit immediate suitable > - for an addi instruction. If that's the case, force it into > - a register. */ > + /* TEMP2 and/or ALT might not fit into a signed 12 bit immediat= e > + suitable for an addi instruction. If that's the case, force= it > + into a register. */ > if (!SMALL_OPERAND (INTVAL (temp2))) > temp2 =3D force_reg (mode, temp2); > + if (!SMALL_OPERAND (INTVAL (alt))) > + alt =3D force_reg (mode, alt); > > riscv_emit_binary (PLUS, temp1, cons, temp2); > emit_insn (gen_rtx_SET (dest, > diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c b/gcc/testsuit= e/gcc.target/riscv/zicond-ice-2.c > new file mode 100644 > index 000000000000..ffd8dcb5814e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gc_zicond -mabi=3Dlp64d" { target { rv64 }= } } */ > +/* { dg-options "-march=3Drv32gc_zicond -mabi=3Dilp32d" { target { rv32 = } } } */ > + > +#define SOME_NUMBER 0x1000 > + > +unsigned long > +d (unsigned long n) > +{ > + return n > SOME_NUMBER ? SOME_NUMBER : n; > +} > > base-commit: 78f636d979530c8a649262dbd44914bdfb6f7290 > -- > 2.42.0 >