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From: Kito Cheng <kito.cheng@gmail.com>
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Cc: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com
Subject: Re: [PATCH] RISC-V: Enable movmisalign for VLS modes
Date: Tue, 29 Aug 2023 21:54:00 +0800	[thread overview]
Message-ID: <CA+yXCZBPb+7ihaNrSXpHs1Oj0rHvF=Simo7LRcV3agg62HrJjQ@mail.gmail.com> (raw)
In-Reply-To: <20230829100738.2479550-1-juzhe.zhong@rivai.ai>

> +    /* To support misalign data movement, we should use
> +       minimum element alignment load/store.  */
> +    unsigned int size = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode));
> +    poly_int64 nunits = GET_MODE_NUNITS (<MODE>mode) * size;
> +    machine_mode mode = riscv_vector::get_vector_mode (QImode, nunits).require ();
> +    operands[0] = gen_lowpart (mode, operands[0]);
> +    operands[1] = gen_lowpart (mode, operands[1]);
> +    if (MEM_P (operands[0]) && !register_operand (operands[1], mode))
> +      operands[1] = force_reg (mode, operands[1]);

Does force_reg safe for movmisalign?

  reply	other threads:[~2023-08-29 13:54 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-29 10:07 Juzhe-Zhong
2023-08-29 13:54 ` Kito Cheng [this message]
2023-08-29 14:23   ` Jeff Law
2023-08-29 22:27     ` 钟居哲
2023-08-30  1:29       ` Li, Pan2

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