From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x2b.google.com (mail-oa1-x2b.google.com [IPv6:2001:4860:4864:20::2b]) by sourceware.org (Postfix) with ESMTPS id C1C1C385B522 for ; Mon, 30 Jan 2023 16:53:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C1C1C385B522 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-15085b8a2f7so15801739fac.2 for ; Mon, 30 Jan 2023 08:53:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=XT+babwuzmEJQpxsFv6pc+9yJzHbCEsZ/QOXEnUPsWU=; b=XOiyoRc24e7zbA+A2vy+LFn3uutFycxA4m66lCOgLr5wT/3bIzyJdZviztWGgMVaIV ShFLNIlFcW9YWdCQhjg1wJr8jFiXlkjO5Z3L2LNe4vFBToyZxD4Pu6YtBs0gKjSwhY5Y 2LhNAh++tV38xBu+nxqkFGbNb8rCTK8nHwMNTJ2rDmfNQiq5IOx3onhMPZzN7+eRE5Qb /Ad5LzBFHzN7U3tHyB+txc/wWLTwYCsodmrKcZoLy1YZOJHz04rtSXdvKrCBflGgIQ67 Af7i8/stPtwSVdPwWhHcS+plM80E6JDs8ikniYcohWoRqrlyHyeRBNZ17EgYAw9FUjwN O0VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=XT+babwuzmEJQpxsFv6pc+9yJzHbCEsZ/QOXEnUPsWU=; b=FclM0PmFiP0U9dW1zcncmyrmfhJLON+i97iz1E0OF1aP1XZCr5yuGh2CTSmwjkG4ZC +vBBKWXCrm6+O8dpcCQ51NwvPGTwChmSfUeLZyxSv2BxdqbU+z/Rxr4mUm8Z8wbi5Jys ATOXRszTpceHsi/TczKwQFc0esCjmRhuD2c//GaZLkHkB8/xhnfmq3cFWY83mjRHmHNS yo8SnATdoek7prlApcOMpvuiOQpKOaId5TBHIuUBWCf7zzEdYeaG3GLaxIXMuZzrAwkg iUQZTpABwNKAhi1WZ87qiab34j5BQf0p2s6kj0rts1t9sGcN1hMq64SZeyvY4hOLr/ic 3wbg== X-Gm-Message-State: AFqh2krUFr5ADjGckkvgWHdspMpAyk49gEdmqNOhujJngWToEtg4r29H bzhxXzGRaYPZ2TR/GkNlhBxQTzjYeW0Kl7PHlqk= X-Google-Smtp-Source: AMrXdXsbHQ1ONmZlkr1IrakPjLHuQaRpWBO/MI4WqmIKxn6lhe4in6e2N4tYI7LAVhbKX9Dz2PQo92zmb3pHKuzEcC4= X-Received: by 2002:a05:6870:a101:b0:15f:22b4:159c with SMTP id m1-20020a056870a10100b0015f22b4159cmr4334984oae.11.1675097593006; Mon, 30 Jan 2023 08:53:13 -0800 (PST) MIME-Version: 1.0 References: <20230129153721.220810-1-juzhe.zhong@rivai.ai> In-Reply-To: <20230129153721.220810-1-juzhe.zhong@rivai.ai> From: Kito Cheng Date: Tue, 31 Jan 2023 00:53:01 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Add indexed loads/stores constraints testcases To: juzhe.zhong@rivai.ai Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=1.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: committed, thanks! On Sun, Jan 29, 2023 at 11:37 PM wrote: > > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c: New test. > > --- > .../riscv/rvv/base/vlxei-vsxei-constraint-1.c | 121 ++++++++++++++++++ > 1 file changed, 121 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c > new file mode 100644 > index 00000000000..56e599391fd > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c > @@ -0,0 +1,121 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +#include "riscv_vector.h" > + > +/* > +** f1: > +** vsetivli\s+zero,4,e32,mf2,tu,m[au] > +** vlse32\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero > +** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero > +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ > +** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ > +** ret > +*/ > +void f1 (void * in, void * in2, void *out) > +{ > + vfloat32mf2_t v = __riscv_vlse32_v_f32mf2 (in, 0, 4); > + vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4); > + vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_tu (v, in, index, 4); > + __riscv_vsoxei8_v_f32mf2 (out, index, v2, 4); > +} > + > +/* > +** f2: > +** vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vlm\.v\s+v[0-9]+,\s*0\([a-x0-9]+\) > +** vsetivli\s+zero,4,e32,mf2,\s*t[au],\s*m[au] > +** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero > +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+,v0.t > +** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ > +** ret > +*/ > +void f2 (void * in, void * in2, void *out) > +{ > + vbool64_t mask = *(vbool64_t*)in; > + asm volatile ("":::"memory"); > + vfloat32mf2_t v = __riscv_vlse32_v_f32mf2 (in, 0, 4); > + vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4); > + vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_m (mask, in, index, 4); > + __riscv_vsoxei8_v_f32mf2 (out, index, v2, 4); > +} > + > +/* > +** f3: > +** vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vlm\.v\s+v[0-9]+,\s*0\([a-x0-9]+\) > +** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*tu,\s*mu > +** vlse32\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero > +** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero > +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+,v0.t > +** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ > +** ret > +*/ > +void f3 (void * in, void * in2, void *out) > +{ > + vbool64_t mask = *(vbool64_t*)in; > + asm volatile ("":::"memory"); > + vfloat32mf2_t v = __riscv_vlse32_v_f32mf2 (in, 0, 4); > + vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4); > + vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_tumu (mask, v, in, index, 4); > + __riscv_vsoxei8_v_f32mf2 (out, index, v2, 4); > +} > + > +/* > +** f4: > +** vsetivli\s+zero,4,e8,mf8,tu,\s*m[au] > +** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),zero > +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ > +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ > +** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ > +** ret > +*/ > +void f4 (void * in, void * in2, void *out) > +{ > + vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4); > + vint8mf8_t v = __riscv_vluxei8_v_i8mf8 (in, index, 4); > + vint8mf8_t v2 = __riscv_vluxei8_v_i8mf8_tu (v, in, index, 4); > + __riscv_vsoxei8_v_i8mf8 (out, index, v2, 4); > +} > + > +/* > +** f5: > +** vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vlm\.v\s+v[0-9]+,\s*0\([a-x0-9]+\) > +** vsetivli\s+zero,4,e8,mf8,t[au],m[au] > +** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),zero > +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+,v0.t > +** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ > +** ret > +*/ > +void f5 (void * in, void * in2, void *out) > +{ > + vbool64_t mask = *(vbool64_t*)in; > + asm volatile ("":::"memory"); > + vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4); > + vint8mf8_t v = __riscv_vluxei8_v_i8mf8 (in, index, 4); > + vint8mf8_t v2 = __riscv_vluxei8_v_i8mf8_m (mask, in, index, 4); > + __riscv_vsoxei8_v_i8mf8 (out, index, v2, 4); > +} > + > +/* > +** f6: > +** vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au] > +** vlm\.v\s+v[0-9]+,\s*0\([a-x0-9]+\) > +** vsetivli\s+zero,4,e8,mf8,tu,mu > +** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),zero > +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ > +** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+,v0.t > +** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+ > +** ret > +*/ > +void f6 (void * in, void * in2, void *out) > +{ > + vbool64_t mask = *(vbool64_t*)in; > + asm volatile ("":::"memory"); > + vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4); > + vint8mf8_t v = __riscv_vluxei8_v_i8mf8 (in, index, 4); > + vint8mf8_t v2 = __riscv_vluxei8_v_i8mf8_tumu (mask, v, in, index, 4); > + __riscv_vsoxei8_v_i8mf8 (out, index, v2, 4); > +} > -- > 2.36.3 >